I wish to incorporate a onehot decoder for my registers so that only one register is accessing the bus at a time. I also wish to introduce a memory system that uses a program counter to navigate through my memory. The memory is an address system that stores each instruction code.

This is what my current code looks like

module datapath $($

input clk$,$

input rst$,$

input $[15$:$0]$ instruction,

input $[1$:$0]$ addSub

$)$;

$//$ Register enables and tristate buffers

wire $[15$:$0]$ Rout;

wire $[15$:$0]$ bus;

wire $[15$:$0]$ myWire $[15$:$0]$;

$//$ Control circuit control$\_$signal

controlcircuit control$\_$signal $($

$.$clk$($clk$),$

$.$rst$($rst$),$

$.$instruction$($instruction$),$

$.$reg$\_$enable$($enableRegisterin$),$

$.$tri$\_$enable$($enableRegistersout$)$

$)$;

$//$ Register Generation

genvar i;

generate

for $($i $=0$; i $<8$; i $=$ i $+1)$ begin: registerGeneration

$//$ Registers

myreg regin $($

$.$clock$($clk$),$

$.$x$($bus$),$

$.$enable$($Rin$[$i$]),$

$.$y$($myWire$[$i$]),$

$.$rst$($rst$)$

$)$;

$//$ Tristate buffer

tristatebuffer regout $($

$.$a$($myWire$[$i$]),$

$.$enable$($Rout$[$i$]),$

$.$b$($bus$)$

$)$;

end

$//$ Register A

myreg regA $($

$.$clock$($clk$),$

$.$x$($bus$),$

$.$enable$($Rin$[8]),$

$.$y$($myWire$[8]),$

$.$rst$($rst$)$

$)$;

$//$ ALU

ALU alu $($

$.$a$($myWire$[8]),$

$.$b$($bus$),$

$.$addSub$($addSub$),$

$.$result$($myWire$[9])$

$)$;

$//$ Register G

myreg regG $($

$.$clock$($clk$),$

$.$x$($myWire$[9]),$

$.$enable$($Rin$[9]),$

$.$y$($myWire$[10]),$

$.$rst$($rst$)$

$)$;

$//$ Tristate buffer for RegG output

tristatebuffer regGout $($

$.$a$($myWire$[10]),$

$.$enable$($Rout$[10]),$

$.$b$($bus$)$

$)$;

endgenerate

endmodule

module myreg $($

input clock,

input $[15$:$0]$ x$,$

input enable,

output reg $[15$:$0]$ y$,$

input rst

$)$;

always @$($posedge clock or posedge rst$)$

begin

if $($rst$)$

y $<=16\text{'}$b$0$;

else if $($enable$)$

y $<=$ x;

end

endmodule

module ALU $($

input $[15$:$0]$ a$,$

input $[15$:$0]$ b$,$

input $[1$:$0]$ addSub,

output reg $[15$:$0]$ result

$)$;

always @$(*)$

begin

case $($addSub$)$

$2\text{'}$b$00$: result $=$ a $+$ b; $//$ add

$2\text{'}$b$01$: result $=$ a $-$ b; $//$ subtract

$2\text{'}$b$10$: result $=$ a $^$ b; $//$ xor

default: result $=16\text{'}$b$0$; $//$ default to $0$

endcase

end

endmodule

module Next$\_$State $($instruction$,$current$\_$state,next$\_$state$)$;

input $[15$:$0]$instruction;

input $[3$:$0]$current$\_$state;

output $[3$:$0]$reg next$\_$state;

case$($current$\_$state$)$

$4\text{'}$b$0000$:begin

case$($instruction$[15$:$12])$

$4\text{'}$b$0000$: next$\_$state$=4\text{'}$b$0001$;

$4\text{'}$b$0001$: next$\_$state$=4\text{'}$b$0010$;

$4\text{'}$b$0010$: next$\_$state$=4\text{'}$b$0011$;

$4\text{'}$b$0011$: next$\_$state$=4\text{'}$b$0011$;

$4\text{'}$b$0100$: next$\_$state$=4\text{'}$b$0011$;

end

$4\text{'}$b$0001$: next$\_$state$=4\text{'}$b$1000$;

$4\text{'}$b$1000$: next$\_$state$=4\text{'}$b$0000$;

$4\text{'}$b$0010$: next$\_$state$=4\text{'}$b$0000$;

$4\text{'}$b$0011$: next$\_$state$=4\text{'}$b$0100$;

$4\text{'}$b$0100$: next$\_$state$=4\text{'}$b$0101$;

$4\text{'}$b$0101$: next$\_$state$=4\text{'}$b$0000$;

endmodule

module tristatebuffer $($

input $[15$:$0]$ a$,$

output reg $[15$:$0]$ b$,$

input enable

$)$;

always @$(*)$

begin

if $($enable$)$

b $=$ a;

else

b $=16\text{'}$bZ; $//$ tri$-$state

end

endmodule

module tristateenable$($state$,$ instruction, Rin, Rout, addSub$)$;

input $[3$:$0]$ state;

input $[15$:$0]$ instruction;

input $[1$:$0]$ branch;

output $[15$:$0]$ Rin, Rout;

output addSub;

wire$[3$:$0]$ triReg, triRegEnable

oneHot writeDemux$(.$select$($triReg$),.$out$($triStateWire$))$

$//$Gout$,$Rout$7-0$

oneHot readDemux$(.$select$($RegEnable$),.$out$($triRegEnableWire$))$

$//$Gin$,$Ain,Rin$7-$Rin$0$

always@$($state$)$ begin

case$($state$)$

$4\text{'}0001$: begin$//$load $1$

$//$triReg $=4\text{'}1010//$Data trireg enable

RegEnable $=$ instruction$[11$:$8]//$Rxin enable

branch $=2\text{'}$b$00$

end

$4\text{'}1000$: begin$//$load $2$

triReg $=4\text{'}1010//$Data trireg enable

branch $=2\text{'}$b$00$

end

$4\text{'}0010$: begin$//$move

triReg $=$ instruction$[7$:$4]//$Rxout

RegEnable $=$ instruction$[11$:$8]//$Ryin

branch $=2\text{'}00$

end

$4\text{'}0011$: begin$//$add sub xor $1$

triReg $=$ instruction$[11$:$8]//$Rxout

RegEnable $=4\text{'}1000//$Ain

end

$4\text{'}0100$: begin$//$ add sub xor $2$

triReg $=$ instruction$[7$:$4]$

RegEnable $=4\text{'}1001$

if $($instruction$[15$:$12]=4\text{'}$b$0011)$

addSub $=2\text{'}$b$01$;

else if $($instruction$[15$:$12]=4\text{'}$b$0010)$

addSub $=2\text{'}$b$10$;

else

addSub $=2\text{'}$b$00$;

end

$4\text{'}0101$: begin$//$ add sub xor $3$

triReg $=4\text{'}1001$

RegEnable $=$ instruction$[5$:$2]$

module instruction$\_$memory$($address$,$ data$)$;

input $[3$:$0]$ address;

output $[15$:$0]$ data;

$//$have to grab instruction then grab number

$//$load $0000$

$//$move $0001$

$//$add $0010$

$//$XOR $1000$

$//$REG$00000$

$//$REG$10001$

always @$($address$)$ begin $//$hard coded instruction $-$ not write to memory