I would like at least one of the rows filled with what it asks with descriptions of how you get said row values. If you can do more than one, fantastic! If you do the whole table, could you also help me with the follow-up question? I would like to wrap my head around the logic of the questions.

Question/Task: A CPU uses a 12-bit logical address with the first 4-bits for the page number and 8-bits for the offset to access 2kb of physical memory. Given the following TLB Table and Page Table. Complete the following table. Base Register points to the page table in physical memory. All entries in hexadecimal. Inv = Valid/Invalid Bit is Set to Invalid

TLB Page Number	Frame Number
0	3
4	1
5	2
9	0

Base Register	Frame	Base Register	Frame
+0	3	+8	Inv
+1	Inv	+9	0
+2	5	+A	4
+3	1	+B	Inv
+4	2	+C	Inv
+5	Inv	+D	Inv
+6	Inv	+E	6
+7	Inv	+F	7

Logical Address	Page Number - p	Offset - d	Frame Number	Hit?	Physical Address
0x400
0x3FF
0xA01
0x500
0x910

Follow-Up Question: Given the above as a starting point, what is the resulting Page and TLB after the following address requests? The table is updated using FIFO page replacement and the pages were loaded in ascending order by frame number (i.e. frame 0 is the oldest page, 7 the most recently added). How many page faults occur?

0x401, 0x402, 0x6A0, 0x6A1, 0x403, 0x402,0x902,0xF00, 0x4FF,0x500

TLB Page Number	Frame Number

Base Register	Frame	Base Register	Frame
+0		+8
+1		+9
+2		+A
+3		+B
+4		+C
+5		+D
+6		+E
+7		+F