If a variable is allocated to a register, then the processor does not need to issue a memory reference to get the value of that variable. In the following loop, suppose none of the array elements are allocated to registers, but all scalar variables are in registers. Assuming the same cache in Problem 5, what is the highest possible cache miss ratio when the processor executes the following loop? What is the highest possible cache hit ratio when the processor executes the following loop? You must clearly explain how you derive your answer, taking into account of possibilities of data layout in practice. (We assume that the first reference to each array element is a cache miss.)

for (i=1; i for (t=0; t<256; t++) {

D[i] = (A[i]+B[i])/C[i];

A[i]= (E[i]-D[i])/3.0;

}

}

Question 5 for context: Suppose the physical address is 30-bit long and the cache size is 8K (K=1024) words. How many bits must the cache index have if the cache is direct- mapped? How many bits must the tag have?