If the instruction execution is pipelined, each pipeline stage requires additional $20$ ps for the

registers between the pipeline stages. Cycle time refers to the time an instructions needs for

execution. Latency is the number of clock cycles it takes for an individual instruction to have

its data available for use by another instruction after it starts its execution. Throughput is the

number of instructions completed per time unit.

i$)$ The processors are implemented in a non$-$pipelined, single$-$cycle fashion. Determine cycle

time, latency of an instruction, and throughput for each processor.

ii$)$ The processors are implemented in a pipelined fashion. Determine cycle time, latency of

an instruction, and throughput for each processor.

iii$)$ If you could split one of the pipeline stages into two equal halves, which one would you

choose? What is the new cycle time, latency, and throughput for each processor?

iv$)$ Assume the distribution of instructions that run on the processor is:

$50\%$ ALU

$25\%$ BEQ

$15\%$ LW

$10\%$ SW

Assuming there are no stalls or hazards, what is the utilization of the data memory and

the register block$$s write port? We consider the utilization in percentage of clock cycles

used.

$1$