IF YOU DONT USE VHDL I WILL NOT GIVE THUMBS UP. DO NOT UPLOAD USING VERILOG MY TEACHER DOESNT ACCEPT VERILOG. HE ONLY WANTS VHDL! PLEASE READ CAREFULLY AND MAKE SURE ITS UPLOADED AS ONLY A VHDL FILE AS WELL AS UPLOAD THE TEST BENCH FILE.

ONLY USING VHDLVHDL) In the block diagram shown below, the ALU can perform the following 16 operations: REGISTER 1 ALU REGISTER 3 REGISTER 2 AND NAND OR NOR XOR XNOR NOT Addition Subtraction Logical Right Shift Logical Left Shift Arithmetic Right Shift Arithmetic Left shift Greater than Less than Equal to Load data into the Registers 1 and Register 2 and then read and send those data to the ALU as shown in the block diagram. Use a decoding scheme in the ALU to choose the operation out of the 16 operations mentioned above. The output of the ALU is being saved and read from the Register 3