If you use system Verilog this will still work, or you can change the always @ $(*)$ to always$\_$comb and

reg to logic.

Problem $1)$ Complete the code above for all $26$ letters and $10$ numbers not just the ones you need for

your test.

Problem $2)$ Next you need to write the parent module in which the code above is an instance. This

parent module that instantiates ASCII$27$Seg to display $$Hello OLH$($replace with your initials$)$ should

look something like this in Verilog.

Note, if you run a simulation of ASCIICodes you must force Kkey$0$ to $0$ or $1$ for it to choose a message.

You can choose a ASII radix in ModelSim which will cause it to show $$Hello$$ and $$OLH$$ for the

message, but you might as well use a radix of binary for the HexSeg variables. They are not ASCII

codes and will not look in ModelSim like the letter or number.