I'm working with Lt spice

Part1: 6 to 3 High Priority Encoder (schematic) In this part you will be responsible for designing the 6 to 3 Low Priority Encoder shown in the following figure. Figure 1: 6 to 3 high priority encoder block diagram 1. Write the required Boolean expression for the 6 to 3 High Priority Encoder. Also show detailed gate level for the 6 to 3 High Priority Encoder . The gate level (Using AND/OR/INV gates) design should show all inputs and outputs. 2. Show the transistor level design of the encoder. In your design you have the full freedom to arrange the transistors to implement the decoder functionality. 3. Size all the transistors to make sure that the rise and the fall delays are the same. 4. For the implemented design draw the input waveforms such that all the possible combinations are tested. 5- Report the encoder worst case delay