Implement the ALU shown in Figure 1 using Verilog, the ALU must be implemented using structural models only, and should meet the following requirements. Register File Reg A Reg B Reg C Reg D Opi Op2 Op1 Sel 2 Op2 Sel 2 Operation ALU Result Status Figure 1. ALU model There is a control line named operation Operation is responsible for selecting the operation to be performed by the ALU The ALU has two 8-bit input Ports (Op1 and Op2). Op1 and Op2 values are fetched from the registers (A, B, C and D) based on Op1 Sel and Op2 Sel control lines. As shown in Table 1. Operand Selection 00 01 10 Selected Register A B C D 11 Table 1. Register Select . The ALU has two output registers: result and status. Result is an 8-bit register while status is a 3- bit register. The operations being performed in the ALU are based on table 2. Operation ALU operation Result register Status Register affected bits 0000 0001 0010 Z, C ZV 0011 0100 --- 0101 Z 0110 Z One's complement for Op1 One's complement for Op1 Two's complement for Op1 Two's complement for Op1 Addition Op1 + Op2 Subtraction Op1 - Op2 Comparator 0 { if Op1 > Op2} 1{if Op1 = Op2} 2 {if Op1