IN LOGISIM ONLY

There are three parts to this assignment, based on the three circuits shown below.

The purpose of this assignment is to create a 3-bit decode logic, mux, and a 4-bit full adder from only logic gates. Using the model of a 2 bit decoder that we reviewed in class, extend this design to 3 bits of input using the same gate technology shown in the lecture. Additionally, using the model of the 2 bit selector mux that we reviewed in class, extend this design to a 3 bit selector mux using the same gate technology shown in the lecture. Using the gate technology shown in the lecture, extend this 1-bit full adder to 4 bits. Be sure to appropriately group the A operand bits together, B operand bits together, and sum bits together in order from MSB to LSB (left to right).