In order to produce a $4-$bit Frame Check Sequence $($FCS$)$ for an $11-$bit message, a Cyclic

Redundancy Checker $($CRC$)$ is built. The polynomial generator is $x_4+x_3+1.$

$(5$ marks$)$

a$)$ Draw the shift register circuit that would perform this task

b$)$ Encode the data bit sequence $10011010100($the leftmost bit is the least

significant$)$ using the generator polynomial and give the code word.

c$)$ Encode the data bit sequence $10010010100($the leftmost bit is the least

significant$)$ using the generator polynomial and give the code word.