In the circuit below, the wire between inverter x and y is 0.15m wide and 0.05mm long. 10fF X Y 100fF A. Assume the sheet resistance of wire is 0.1/. What is the total resistance of the wire? B. The on resistance of the inverter with input capacitance of 10fF is 1000. The unit capacitance of the wire is 2fF/m. How large should the x and y (normalized to 10fF) be to get the shortest path delay? What is the shortest delay? Assume the wire can be modeled with single segment model as shown in the figure, and- = 1 Cgate C. Size the x and y for shortest delay without the wire resistance and capacitance. Compare your result with part B. In the circuit below, the wire between inverter x and y is 0.15m wide and 0.05mm long. 10fF X Y 100fF A. Assume the sheet resistance of wire is 0.1/. What is the total resistance of the wire? B. The on resistance of the inverter with input capacitance of 10fF is 1000. The unit capacitance of the wire is 2fF/m. How large should the x and y (normalized to 10fF) be to get the shortest path delay? What is the shortest delay? Assume the wire can be modeled with single segment model as shown in the figure, and- = 1 Cgate C. Size the x and y for shortest delay without the wire resistance and capacitance. Compare your result with part B.