. In the following circuit, AND gates have a delay of 8nsec, OR gates have a delay of 10nsec, and XOR gates have a delay of 12nsec. The input of the circuit goes from xyz=001 to xyz=100 at time t=0. Determine the signals at the outputs from t=0 to t=50nsec. Use a waveform diagram or a table.

We haven't gone over this in class at all so a clear explanation of the steps would help out a lot. Thanks!

6. In the following circuit, AND gates have a delay of 8nsec, OR gates have a delay of 10nsec, and XOR gates have a delay of 12nsec. The input of the circuit goes from xyz 001 to xyz 100 at time t-0. Determine the signals at the outputs from t-0 to t-50nsec. Use a waveform diagram or a table. xe y