In the following Verilog code:

always @$($posedge clk$)$ begin if $($reset$)$ begin

count $0$;

end else begin

count $$ count $+1$ ;

if $($count $==4\text{'}h$ F$)$ begin count $0$;

end

end

end

What will be the value of count after $12$ clock cycles if reset is $0?$