In the following, we have a code fragment of LEGV8 assembly: STUR X16, [X6, #12] LDUR X16, [X6, #8] SUB X7, X5, X4 CBZ X7, Label X1, X4 ADD X5, SUB X5, X15, X4 Assume we run this code on a pipeline CPU that has only one memory for both instructions and data. In this case, there could be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data. 1- Show where to insert NOPs in the code above to avoid the structural hazard. 2- In your opinion, is there any solution to reduce the number NOPs? Like reordering the instructions. 3- Do you think that we must handle this structural hazard in hardware? You know that data hazards can be avoided by inserting NOPs between assembly instructions. Can we do the same with this structural hazard? If so, explain how. If not, explain why not. 4- If we run the code above on a single-cycle computer, what kind of hazards are there