In this assignment, you will complete the tables in the provided Excel file. For the instructions listed in the spreadsheets, find out the cycle numbers when an instruction is issued, starts the execution, completes the execution, writes the result, and optionally is committed Assume the processor has the following FUs Cycles in EX Num of FUs Num of Resv. Stations FU Type Integer FP Adder FP Multiplier Loads Stores * See the explanations below 1 * Branches are integer operations. They are resolved in EXE and do not need WB. Leave WB stage blank for branches The branches in the code are taken. The target instruction(s) can be issued the cycle after the branch is issued (because of a very effective BTB). Loads and stores share an addressing unit (not the integer FU) to calculate address, in the program order and when base registers are ready. Loads take one cycle to calculate address and one cycle to access memory. Consider both cycles as EXE for loads and the 2-stage process is pipelined Stores take one cycle to calculate address in EXE and one cycle to write to memory in WB (or in Commit). They may wait between two stages for the data to be stored. The stores do not use CDB in WB even if the write takes place in WB An instruction can wait for CDB between EXE and WB . . . If there is a structural hazard, the earliest instruction in program order has priority. 1. Non-speculative Tomasulo's algorithm (30 points) In this exercise, assume FP FUs are NOT pipelined. There is no speculation. 2. Tomasulo's algorithm with speculation (30 points) Assume the following in this exercise . FP FUs are pipelined. The initiation interval is 1 for both FP adder and multipliers * Support speculation. . There are enough number of entries in the reorder buffer. So the reorder buffer does not cause structural hazards In this assignment, you will complete the tables in the provided Excel file. For the instructions listed in the spreadsheets, find out the cycle numbers when an instruction is issued, starts the execution, completes the execution, writes the result, and optionally is committed Assume the processor has the following FUs Cycles in EX Num of FUs Num of Resv. Stations FU Type Integer FP Adder FP Multiplier Loads Stores * See the explanations below 1 * Branches are integer operations. They are resolved in EXE and do not need WB. Leave WB stage blank for branches The branches in the code are taken. The target instruction(s) can be issued the cycle after the branch is issued (because of a very effective BTB). Loads and stores share an addressing unit (not the integer FU) to calculate address, in the program order and when base registers are ready. Loads take one cycle to calculate address and one cycle to access memory. Consider both cycles as EXE for loads and the 2-stage process is pipelined Stores take one cycle to calculate address in EXE and one cycle to write to memory in WB (or in Commit). They may wait between two stages for the data to be stored. The stores do not use CDB in WB even if the write takes place in WB An instruction can wait for CDB between EXE and WB . . . If there is a structural hazard, the earliest instruction in program order has priority. 1. Non-speculative Tomasulo's algorithm (30 points) In this exercise, assume FP FUs are NOT pipelined. There is no speculation. 2. Tomasulo's algorithm with speculation (30 points) Assume the following in this exercise . FP FUs are pipelined. The initiation interval is 1 for both FP adder and multipliers * Support speculation. . There are enough number of entries in the reorder buffer. So the reorder buffer does not cause structural hazards
