In this exercise, we assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline, full forwarding, and a predict-taken branch predictor. LW Labell: BEQ LW R2, 0 (R1) R2, RO, Label2 #Not taken once, then always taken R3, 0 (R2) BEQ R3, RO, Labell #Always taken ADD R1, R3, R1 Label2: SW R1, 0 (R2) ADD R4, R5, R6 Draw the pipeline execution diagram for this code, assuming that branches execute in the EX stage.