In this exercise, we examine how data dependences affect execution in the basic 5-stage pipeline described in Chapter 4.5 (An overview of pipelining). Problems in this exercise refer to the following sequence of instructions: add r3, rl, r2 add r2, rl, r3 add r2, r2, r3 Also, assume registers can be read and written in the same cycle and the following cycle times for each of the options related to forwarding: Without Forwarding 200ps With Full Forwarding 350ps With ALU-ALU Forwarding Only 300ps a. Indicate ALL dependences and their type (RAW/WAR/WAW). b. Assume there is no forwarding in this pipelined processor. Draw a pipeline execution diagram. Insert nop instructions to eliminate any hazards. c. Assume there is full forwarding. Draw a pipeline execution diagram. Insert nop instructions to eliminate any hazards. d. What is the total execution time of this instruction sequence without forwarding and with full forwarding? What is the speedup achieved by adding full forwarding to a pipeline that had no forwarding? Assume there is ALU-ALU forwarding only (no forwarding from the MEM to the EX stage). Draw a pipeline execution diagram. Insert nop instructions to eliminate any hazards. f. What is the total execution time of this instruction sequence with only ALU-ALU forwarding? What is the speedup over a no-forwarding pipeline