In this exercise, we examine how resource hazards, control hazards, and Instruction Set Architecture (ISA) design can affect pipelined execution. Problems in this exercise refer to the following fragment of MIPS code: sw r16, 12 (r6) lw r16, 8(r6) beg r5, r4, Label # Assume r5 != r4 add r5, rl, r4 slt r5, r15, r4 Unless stated, all problems are independent scenarios. Also, assume registers can be read and written in the same cycle and the following cycle times for each of the options related to forwarding: WB IF 200ps ID 100ps EX 150ps MEM 250ps 100ps a. For this problem, assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. Draw a pipeline execution diagram. What is the total execution time of the instruction sequence? b. For this problem, assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. If we change load/store instructions to use a register (without an offset) as the address, these instructions no longer need to use the ALU. As a result, every instruction will only utilize either MEM or EX stage, and the pipeline has only 4 stages. Draw a pipeline execution diagram to reflect this change. Assuming this change does not affect clock cycle time, what is the total execution time of the instruction sequence? What is the speedup of this change compared to part a? c. For this problem, assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. If we only have one memory (for both instructions and data), there is a structural hazard every time we need to fetch an instruction in the same cycle in which another instruction accesses data. To guarantee forward progress, this hazard must always be resolved in favor of the instruction that accesses data. Draw a pipeline execution diagram. What is the total execution time of this instruction sequence in the 5-stage pipeline that only has one memory? d. We have seen that data hazards can be eliminated by adding nops to the code. Can you do the same with the structural hazard described in part c? Why? e. Assuming stall-on-branch and no delay slots and branch outcomes are determined in the ID stage instead of EXE stage, draw a pipeline execution diagram. Insert nops if necessary. What is the total execution time of the instruction sequence? In this exercise, we examine how resource hazards, control hazards, and Instruction Set Architecture (ISA) design can affect pipelined execution. Problems in this exercise refer to the following fragment of MIPS code: sw r16, 12 (r6) lw r16, 8(r6) beg r5, r4, Label # Assume r5 != r4 add r5, rl, r4 slt r5, r15, r4 Unless stated, all problems are independent scenarios. Also, assume registers can be read and written in the same cycle and the following cycle times for each of the options related to forwarding: WB IF 200ps ID 100ps EX 150ps MEM 250ps 100ps a. For this problem, assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. Draw a pipeline execution diagram. What is the total execution time of the instruction sequence? b. For this problem, assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. If we change load/store instructions to use a register (without an offset) as the address, these instructions no longer need to use the ALU. As a result, every instruction will only utilize either MEM or EX stage, and the pipeline has only 4 stages. Draw a pipeline execution diagram to reflect this change. Assuming this change does not affect clock cycle time, what is the total execution time of the instruction sequence? What is the speedup of this change compared to part a? c. For this problem, assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. If we only have one memory (for both instructions and data), there is a structural hazard every time we need to fetch an instruction in the same cycle in which another instruction accesses data. To guarantee forward progress, this hazard must always be resolved in favor of the instruction that accesses data. Draw a pipeline execution diagram. What is the total execution time of this instruction sequence in the 5-stage pipeline that only has one memory? d. We have seen that data hazards can be eliminated by adding nops to the code. Can you do the same with the structural hazard described in part c? Why? e. Assuming stall-on-branch and no delay slots and branch outcomes are determined in the ID stage instead of EXE stage, draw a pipeline execution diagram. Insert nops if necessary. What is the total execution time of the instruction sequence
