In this experiment, students have to modify the design of their pipelined processor implementation in experiment 7 to test the program shown in Table 3. Note that the program includes two new instructions: SGT (set if greater) and SGTI (set if greater immediate). Examples of these instructions is as follows: SGT R1, R2, R3 /// set R1=1 if R2 > R3, otherwise R1=0 SGTI R1, R2, 100 /// set R1=1 if R2 >100, otherwise R1=0 Unlike previous experiments, this is not a guided experiment, i.e., students are free to make decisions on how to modify all modules in their processor. However, you are not allowed to remove any of the old instructions or start a new implementation from scratch. Students are expected to extend their processor implementation in the lab. Step1: In Table 1, describe the change you did for each file (if any). Note that there are some files where modifications are not needed. Table 1: Verilog files File Modified (yeso)? Changes Description no no no Library439. Exp 2 FA and MUX8_1.v Exp 2 ALUS.v Exp 3 REG32 and MUX32_1.v Exp 3 Decoders and RegFile.v Instruction_memory.v DataMem.v ControlUnit.v Exp6 modules. Exp7 modules. Piplining_Procssor. yes Loaded the program in Table 3 no Step2: In Table 2, add new rows or columns to show the changes you did on the control unit. Highlight your changes in yellow, bold color. Table2: Truth Table for the Control Unit 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 0 0 0 000000 000001 000010 000011 000100 000101 000110 000111 001000 1 0 0 olololololololo 1 olololololololo 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 1 1 1 1 0 1 0 0 0 0 x 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 1 OOOOOOOOOOOOOOOOOXXX 0 0 0 0 0 1 OR 000000 AND 000000 XOR 000000 ADD 000000 NOR 000000 NAND 000000 SLT 000000 SUB 000000 JR 000000 ORI 010000 ANDI 010001 XORI 010010 ADDI 010011 NORI 010100 NANDI 010101 SLTI 010110 SUBI 010111 LW 100011 SW 101011 BEQ 110000 J 110001 JAL 110011 0 0 0 1 0 1 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1000|00|0 10 0 1 0 0 0 0 1 0 0 0 0 0 0 0 ololololololololo 1 0 0 0 0 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 1 1 0 0 1 0 0 0 0 1 1 1 0 0 1 0 0 1 0 1 0 0 0 1 1 1 - 1 0 0 0 X 0 0 0 1 0 XXX ON 0 1 X 0 0 0 1 0 0 0 X 1 1 0 1 0 0 1 1 u Step3: Table 3 shows the Verilog program students are required to use for test. Fill-in the machine codes for this program and also load the instruction memory with this program. Table 3: The content of the instruction memory Address Machine Code 00 LW LW 01 02 03 LW LW 04 SGT SGTI Instruction R1, 12 (RO) R2, 4 (RO) R3, 20 (RO) R4, 28 (RO) R5, R1, R2 R8, R3, 2 R6, R3, R4 R7, R4, 9 R5, 12 (RO) R6, 4 (RO) R7, 20 (RO) R8, 28 (RO) 05 06 07 08 09 SGT SGTI SW SW 10 SW 11 SW Step4: Generate the timing diagram for the program in Table 3, with the below signals (in-order). Note that the test module is already given to you. Clock, reset, enable PC (the output of the program counter) Instruction (the output of the instruction memory) The output of the registers R5, R6, R7, and R8 The readdata, writedata, address, memwrite, and memread signals for the data memory Paste a screenshot of your timing diagram below. Make sure it is clear and readable. Step 5: To make it easier for us to grade your work, in below, copy/paste all modified or new modules in your code. Also, highlight in bold font, the modified lines in the module. For example, if you made changes on the processor module, then copy/paste the entire processor module and highlight only the lines that have been modified. It is okay to use several pages for this step. However, please try your best to show your code in an easy- to-read fashion and avoid large fonts