In this problem you will consider a MIPS application with an instruction make-up described in Table 1. For this problem, assume the standard, 5-stage pipeline described in class. You may assume all loads hit in the Li cache (no extra load delay for misses), and all branches are statically predicted not-taken. Also you may assume that the jump target is calculated during the Register/Decode stage. Calculate the CPI of this program, with the following assumptions (both assumptions together, not individually): No data forwarding paths exist, dependencies must be resolved via stalling. True branch resolution occurs in the Data Memory stage (i.e. correct path fetch can occur in the cycle after DM). Branch/jump delay slots are not implemented. (B) Calculate the CPI of this program, with the following assumptions (both assumptions together, not individually): Data forwarding paths are implemented. Assume the same pipeline as in class. True branch resolution occurs in the Register/Decode stage. Branch/jump delay slots may be used assuming an independent instruction can be found. (Note, you may assume that branches are never data dependent on previous instructions)