IN VHDL

Part A Simple FSMD Simulation

You must use the entity as-is. Do not add or remove port signals or change the types. NOTE: the type inout means that the port signal is bidirectional (i.e., it can be used as an input or output). In the first process, code the state register:

On reset:

Set registers 1 and 2 (r1_reg and r2_reg) to 0 and 1, respectively

Set the initial state to s0

On every rising edge of the clock:

Set the state register to the next state

Set register 1 (r1_reg) to the next value of register 1 (r1_next)

In the second process, code the next-state logic and the Moore output logic in a single process. The state transitions of the FSM are shown as an ASMD chart in Figure 1. As can be seen, since there are no decision boxes, we do not have any Mealy outputs. For additional help on FSMs and FSMDs, see Lab Lecture 4 on TITANium. Once this is complete, create a test bench and simulate the output (see the Test Bench section below for more instructions).

Provided Code:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_unsigned.all;

entity lab_2_part_a is

port(clk, reset : in std_logic;

r1_reg, r2_reg : inout std_logic_vector (7 downto 0));

end lab_2_part_a;

architecture behavioral of lab_2_part_a is

--******************************************

--* TODO: Add FSM states and any signals

--******************************************

begin

--******************************************

--* TODO: State register

--******************************************

process(clk, reset)

begin

end process;

--******************************************

--* TODO: Next-state and Moore logic

--******************************************

process(state_reg)

begin

end process;

end behavioral;