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Introduction In this lab you will explore the design of counters and timers by designing a simple kitchen timer. Requirements The timer has two pushbutton

Introduction

In this lab you will explore the design of counters and timers by designing a simple kitchen timer.

Requirements

The timer has two pushbutton inputs, reset_n and run_stop. It has one 4-bit output, seconds that drives four LEDs and a one-bit output, alarm, that drives one LED. It also has a clock input, clk.

Your timer should operate as follows:

  • The timer can be in one of two states: run=0

    and run=1.

  • run is set to 0 when reset_n is asserted; it is set to the logical inverse of run (not run) when there is a rising edge on run_stop.

  • seconds, the time remaining, is set to the initial timer value (see below) when reset_n is asserted; it is decremented by 1 once per second when run=1 and seconds/=0 (that is, when the timer is running and there is still time remaining).

  • The alarm LED is turned on if run=1 and the time remaining is zero.

    The initial time remaining should be 8+( mod 8) seconds where is the last digit of your BCIT ID. For example, if your Student ID is A01234589 then = 9 and your timer will count from 8 +( 9 mod 8) = 9+ 1 = 10 seconds down to 0.

    Your design should be synchronous all registers should use the same clock and not use asynchronous sets or clears. In particular, reset_n does not directly reset any registers, it is used to determine the value loaded into the register(s) on the next rising edge of the clock.

Pre-Lab

Write the VHDL source code for a kitchen timer that meets the above requirements. It is strongly recommended that you check your VHDL description for syntax errors before the lab. If you dont have access to Quartus or Modelsim you can use the EDA Playground on-line HDL simulator1 .

If youve installed Quartus on your PC you can also follow the procedure below, complete the lab at home and bring your circuit to the lab to have it checked.

Demonstration and Marking

The preparation mark will be based on coming to the lab with a reasonably-complete VHDL code.

The lab instructor will determine the demonstration part of the lab mark by first checking that your circuit:

  • displays the correct value and does not start counting down when reset,

  • counts down when run_stop is pushed, stops when pushed again, restarts when pushed a third time,

  • resets the time remaining and stops when reset_n is pushed,

  • turns on the alarm led when the count reaches zero, and

  • the alarm turns off when run_stop is pushed.

    Then the lab instructor will ask you to make a minor change to the behavior of your design to make sure you understand how it works. For example, the instructor could ask you to modify the initial timer value, the rate at which the timer operates, the operation of the switches (active-high reset, falling-edge run/stop control), etc.

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