its Dld lab. paper.

Program: BSE Subject: Digital Logic Design Time Allowed: 120 Minutes Name: Final Lab (Online), Date: Maximum Marks: 50 Instructor: Adnan Saleem Mughal Registration # Question: (50) Design a synchronous counter, that counts up to 5, by using JK flip flop and display the results on 7-segment display and also give the following details. a) Excitation Table b) State Diagram c) State Table d) IC's Required e) Simulations f) Results snap shots