its urgent . please answer the question in 20 minutes

Assume a pipelined processor with five pipeline stages where each stage takes one clock cycle. Further, assume that the processor has to execute the following instruction sequence: ADD St2, $t3, Sts SUB St5, St2, Sts LW $si, 40(St) LW $53, 32(551) AND $s1, $53, $ti If the procssor only implements stall cycles how many clock cycles would it need to execute the above instructions? If the procssor only implements stall cycles, what would be the average CPI? If the procssor implements stall cycles as well as forwarding, how many clock cycles would it need to execute the above instructions in the most optimu way? If the procssor implements stall cycles as well as forwarding, what would be the CPI if the above instructions were executed in the most optimum way