Ivone on 019: THIS PIODI no longer required.) Verify your model for the diode I/V curve problem using SPICE. See the example SPICE decks below: Example 1: * diode regulated power supply Islam D1 a D_1N4148 MODEL D_IDEAL DIS-In N-0.01 RS-0.01 MODEL D_1N4148 D IS-4.9n N=2 RS=0.5 .DC Isi 2.001m 1eem e.elma .end Plots: dc.v(a) xlog Example 2: Undo changes to netlist diode regulated power supply Isi @ alma Vsi a mv D1 a D 1N4148 .MODEL D_IDEAL DIS-In N-0.01 RS-2.01 . MODEL D 1N4148 D IS-4.9n N=2 RS=0.5 *.DC Isi 2.091m 1080mA e.elma .DC Vsi 100mV 1.5V 18V end Plots -dc. i(si) ylog ylimit 0.0001 10 Have you verified your analysis and included the SPICE deck and a graph in your written work? (yeso) Check Ivone on 019: THIS PIODI no longer required.) Verify your model for the diode I/V curve problem using SPICE. See the example SPICE decks below: Example 1: * diode regulated power supply Islam D1 a D_1N4148 MODEL D_IDEAL DIS-In N-0.01 RS-0.01 MODEL D_1N4148 D IS-4.9n N=2 RS=0.5 .DC Isi 2.001m 1eem e.elma .end Plots: dc.v(a) xlog Example 2: Undo changes to netlist diode regulated power supply Isi @ alma Vsi a mv D1 a D 1N4148 .MODEL D_IDEAL DIS-In N-0.01 RS-2.01 . MODEL D 1N4148 D IS-4.9n N=2 RS=0.5 *.DC Isi 2.091m 1080mA e.elma .DC Vsi 100mV 1.5V 18V end Plots -dc. i(si) ylog ylimit 0.0001 10 Have you verified your analysis and included the SPICE deck and a graph in your written work? (yeso) Check