Just a Verilog code and test bench. I PROMISE to give you 10 thumbs up if you help me with this. THANK YOU

write Verilog programs for adder designs discussed in class, including test-benchesand evaluating the design for various bit-widths. Each of the modules must be parameterized to allow for correctsimulation and synthesis of arbitrary width adders. The main objective of this assignment is to explore the delayof the adders with respect to the bit width. The bit width should be a parameter named WIDTH, and each addershould be tested forW IDT H= 16,32,64,128,256. Please refer to the class lecture notes for the architecture ofthe adders. The testbench for each adder must apply an input pair of the corresponding width that would resultin the maximum delay in computing the final result.Carry Bypass Adder (stage width K = 4)Carry Select Adder (stage width K = 4)Square Root/Variable Width Linear Carry Select Adder (width of 1st stage is K = 4)You must use the Veriloggenerateconstruct,vector of instanceswhen generating each adder type. That is,there will be only 3 Verilog modules, one for each type of adder, with WIDTH parameter to be specified at compiletime, either read in from a file or specified on the command line. All modules for each adder should reside in onefile, but different adders will be in separate files. Hence your submission will include three verilog files.

mplement three different Adder types with Verilog and verify their functionality with test vectors of lengthspecified by the parameter WIDTH.Calculate the worst-case delay forW IDT H= 16,32,64,128,256 in your testbench. Also, make a line graphout of your calculated delays for all different adders. Use the following delays for the logic gates:

Inverter = 58ps

NAND = 94ps

NOR = 94ps

XOR = 156ps

XNOR = 156ps

AND = 130ps

OR = 130ps

AO (ANDOR) = 167psReport includes your simulation result screenshots and one line graph for the 3 adders comparing delays fordifferent values ofW IDT H(as shown in the lecture notes).