just do it in quartus ii and send me screenshot only

library IEEE;

2

use IEEE.STD LOGIC 1164.ALL;

3

Entity declaration

5

entity encoder4to2 is

Port (inputO, inputI, input2, input3 : in

6

STD_LOGIC; -- 4 input signals

output0, outputi: out STD LOGIC);

7

- 2 output signals

8

end encoder4to2;

9

10

-- Architecture declaration

11 architecture Behavioral of encoder4to2 is

12 begin

13

-- Process declaration

14

process (input, input1, input2, input3)

15

begin

output <= 'O'; -- Default value for

16 output0 output1 <= 'O'; -- Default value for

17 output1

18

-- If-else statement to map inputs to

19 outputs

20

if (input = '1') then

21

outputo <= '0'.

2.2

23

elseif (input1 =

Output1 = 'O';, f'y then

24

outputo <= '0'

25

output1 <= '1';

26

elseif (input2 =

"1') then

27

output0 <= '1'

28

output1 <= '0'

29

elseif (input3 =

'1') then

30

outputo <= '1'

31

output1 <= '1';

32

end if;

33

end process;

34 end Behavioral;