Just need a conclusion for this lab. Just a written conclusion nothing else. Thanks.
In this experiment, we practice the display of a counter on seven segments in VHDL programming Objectives: 1) To leam the basic VHDL. programming 2) To leam how to implement VHDL on the physical device 3) To leam how to write VHDL code to display a counter Pre-lab Task: Get familiar with the board. Lab Tasks In this lab, we want to display a counter on the seven segment on Nexys board. For the Nexys board, we need to edit the constraint file before we can start the code implementation using the IDE First create a New project flle with preferred the Project Location, highly recommend to call METE3350/lab2 etc. Like previous lab, make sure all the selections are correct II New Project Wizard - Device Properties Salect the Device and Desian Flow for the Proiect Follow the screen, click Next till Finish. Add the new Source Select VHDL Module Then declare variables for your VHDL design. A window will pop up. elick Yes Now on the space provided, put down the constraints containing Net Name your defined in your VHDL code. and LOC provided. For example. data in with LOC" "G14". where data_in is user defined name in the code. and LOC is the location of the pin. it's predefined. Refer the NET "data_in" LOC = "G14". To start the VHDL programming with a new project Step 1: Start with a new project call lab2 (or whatever name you prefer), this time to select HOL for top level source type as show. Step 2: Right click the project, then select New Source Setp3. Click on Next to select the board as lab1 Step 4: Create a new souce by select VHDL module An.. Caume Whizard - Select Source Tvoe Step o : Now lab2 vhd will be generated, clicking on ic, the window will show as follows 1ibrary TeEE; use IeEE. STD_IoGTC_1164.ALL; use IERE. STD_LoGTC_ARTTH. ATL; use TeEE. STD_LoGC_ UMstareD.AEt; Uncomment the follooing library declaration if instantiating any Xilinx primitives in this code. --11brary citstM; - une tsistM. VComponents.al1; entity test is Port ( A in IND_LotC; B in 520 toatc; Q : out sti_Loatc); end test; architecture Behavioral of test 1s begin end zehavioral; D fip-flops are the most popular type of fip-ffops used in sequential digtal circuits. The D fip-fiop has one data input, one data output, and one clock inout. D fio-fog transfers is data input to the data output when olooked. The truth tabie for D Flip-Fiop VHDL Approach qed -where D is the input Q is the output The following is the how to define d and q at the beginning of oreation of the new project. entity lab2_dff is Port ( cik: in STD_LOGiC: d : in STD_LOGIC: Q: out STD_LOGIC: notq : out STD_LOGiC): end lab2_dft. 4. Bit Shift Repister The Shift Register is a type of sequental logic eircut that can be used for the storage or the transter of binary data. This sequential device loads the data present on its inputs and them moves or "shift it to its output onoe every clock oycle. A shitt register basically consiats of stveral single bt D-Type Data Latches, one for each data bit, either 0 or 1 , oonnected together in a serial type da isy-chain arrangement so the output from one data latch becomes the input of next latch and so on. The basie data movemeet thrawik a whit reaister can be shown as follows Your lab tasks to write VHDL for above logio for both D-Fig-Flog and a 4 bit Shift Register. You should simulate the VHDL at home before the lab and verfy your code during the lab session if possibie. Lab Demo You need to demonstrate display a ONE-bit right or lef Shit Register displaying with LEDO-3, use SW1 as the input data. SWO as the clock. (Hint Your UCF file, assigning oK to SWO, data _in to SW1; reset to Pushbutton 0 , and Q to LED3-LEDO.) You should be ready to answer questions regarding your design and implementation. Before-ab Activities Do the following tasks after leaving the lab: 1. Write the VHDL code for each bulding block developed in this lab. 2. Synthesize the VHDL code to ensure there is no syntax error, and the design is implantable
