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kindly give steps on how to implement the code that you will provide. please be sure not to copy paste the answer drom chat gpt
kindly give steps on how to implement the code that you will provide. please be sure not to copy paste the answer drom chat gpt or anyothher ai thankyou. In this question, you will implement a sequence detector using state machines. a Assuming a singlebit input along with a valid signal that indicates the validity of the input data, and a singlebit output that indicates whether the sequence has been observed or not, implement a structure that performs this task using a Moore state machine. Note that your code should consider overlapping; that is if the input bit sequence is received as in consecutive clocks, the output bit sequence should be sent as b By writing a testbench for this part, verify and validate the functionality of your circuit. c Repeat part a using a Mealy state machine, simulate it and verify its functionality. d Synthesize both circuits, compare the synthesis results, and provide justification. In this question, you will implement and simulate a simple receiver. a First, using MATLAB, generate a number of random bit data. Then design a transmitter that, upon receiving each of these bit data, adds appropriate parity bits and finally sends them in the form of bit data. Finally, you should store these bit data in a file. Also, store the initial bit data in a file for later validation purposes. b Write a Verilog code that receives bit data as input and, based on the parity bits, if the data reception process is correct, it places the bit data on its output and sets the valid signal to high for one clock cycle. Otherwise, it discards the bit data and increments the error output by one. c Now, write a testbench that reads the bit inputs from the file saved in Part A and applies them to the structure in Part B Write the output of the Part B module to a file. Then, in MATLAB or the testbench, compare the output of your module with the initial bit data and verify the functionality of your circuit.
kindly give steps on how to implement the code that you will provide.
please be sure not to copy paste the answer drom chat gpt or anyothher ai thankyou.
In this question, you will implement a sequence detector using state machines.
a Assuming a singlebit input along with a valid signal that indicates the validity of the input data, and a singlebit output that indicates whether the sequence has been observed or not, implement a structure that performs this task using a Moore state machine. Note that your code should consider overlapping; that is if the input bit sequence is received as in consecutive clocks, the output bit sequence should be sent as
b By writing a testbench for this part, verify and validate the functionality of your circuit.
c Repeat part a using a Mealy state machine, simulate it and verify its functionality.
d Synthesize both circuits, compare the synthesis results, and provide justification.
In this question, you will implement and simulate a simple receiver.
a First, using MATLAB, generate a number of random bit data. Then design a transmitter that, upon receiving each of these bit data, adds appropriate parity bits and finally sends them in the form of bit data. Finally, you should store these bit data in a file. Also, store the initial bit data in a file for later validation purposes.
b Write a Verilog code that receives bit data as input and, based on the parity bits, if the data reception process is correct, it places the bit data on its output and sets the valid signal to high for one clock cycle. Otherwise, it discards the bit data and increments the error output by one.
c Now, write a testbench that reads the bit inputs from the file saved in Part A and applies them to the structure in Part B Write the output of the Part B module to a file. Then, in MATLAB or the testbench, compare the output of your module with the initial bit data and verify the functionality of your circuit.
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