kindly provide Just C++ code with explanations.
sample trace
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0 963EF6C0 0 963EF700 0 963EF740 0 963EF780 0 963EF7C0 0 4C9C9800 0 4C9C9840 0 4C9C9880 0 4C9C98C0 0 4C9C9900 0 4C9C9940 0 4C9C9980 0 4C9C99C0 0 4C9C9A00 0 4C9C9A40 0 4C9C9A80 0 4C9C9AC0 0 4C9C9B00 0 4C9C9B40 0 4C9C9B80 0 4C9C9BC0 0 4C9C9C00 0 4C9C9C40 0 4C9C9C80 0 4C9C9CC0 0 4C9C9D00 0 4C9C9D40 0 4C9C9D80 0 4C9C9DC0 0 4C9C9E00 0 4C9C9E40 0 4C9C9E80 0 4C9C9EC0 0 4C9C9F00 0 4C9C9F40 0 4C9C9F80 0 4C9C9FC0 0 3B2E0000 0 3B2E0080 0 3B2E0100 0 3B2E0180 0 3B2E0200 0 3B2E0280 0 3B2E0300 0 3B2E0380 0 3B2E0400 0 3B2E0480 0 3B2E0500 0 3B2E0580 0 3B2E0600 0 3B2E0680 0 3B2E0700 0 3B2E0780 0 3B2E0800 0 3B2E0880 0 3B2E0900 0 3B2E0980 0 3B2E0A00 0 3B2E0A80 0 3B2E0B00 0 3B2E0B80 0 3B2E0C00 0 3B2E0C80 0 3B2E0D00 0 3B2E0D80 0 3B2E0E00 0 3B2E0E80 0 3B2E0F00 0 3B2E0F80 0 08BD6000 0 08BD6080 0 08BD6100 0 08BD6180 0 08BD6200 0 08BD6280 0 08BD6300 0 08BD6380 0 08BD6400 0 08BD6480 0 08BD6500 0 08BD6580 0 08BD6600 0 08BD6680 0 08BD6700 0 08BD6780 0 08BD6800 0 08BD6880 0 08BD6900 0 08BD6980 0 08BD6A00 0 08BD6A80 0 08BD6B00 0 08BD6B80 0 08BD6C00 0 08BD6C80 0 08BD6D00 0 08BD6D80 0 08BD6E00 0 08BD6E80 0 08BD6F00 0 08BD6F80 0 1863D000 0 1863D080 0 1863D100 0 1863D180 0 1863D200 0 1863D280 0 1863D300 0 1863D380 0 1863D400 0 1863D480 0 1863D500 0 1863D580 0 1863D600 0 1863D680 0 1863D700 0 1863D780 0 1863D800 0 1863D880 0 1863D900 0 1863D980 0 1863DA00 0 1863DA80 0 1863DB00 0 1863DB80 0 1863DC00 0 1863DC80 0 1863DD00 0 1863DD80 0 1863DE00 0 1863DE80 0 1863DF00 0 1863DF80 0 D6423040 0 D64230C0 0 D6423140 0 D64231C0 0 D6423240 0 D64232C0 0 D6423340 0 D64233C0 0 D6423440 0 D64234C0 0 D6423540 0 D64235C0 0 D6423640 0 D64236C0 0 D6423740 0 D64237C0 0 D6423840 0 D64238C0 0 D6423940 0 D64239C0 0 D6423A40 0 D6423AC0 0 D6423B40 0 D6423BC0 0 D6423C40 0 D6423CC0 0 D6423D40 0 D6423DC0 0 D6423E40 0 D6423EC0 0 D6423F40 0 D6423FC0 1 B3A38004 1 B3A38084 1 B3A38104 1 B3A38184 1 B3A38204 1 B3A38284 1 B3A38304 1 B3A38384 1 B3A38404 1 B3A38484 1 B3A38504 1 B3A38584 1 B3A38604 1 B3A38684 1 B3A38704 1 B3A38784 1 B3A38804 1 B3A38884 1 B3A38904 1 B3A38984 1 B3A38A04 1 B3A38A84 1 B3A38B04 1 B3A38B84 1 B3A38C04 1 B3A38C84 1 B3A38D04 1 B3A38D84 1 B3A38E04 1 B3A38E84 1 B3A38F04 1 B3A38F84 1 09EC2044 1 09EC20C4 1 09EC2144 1 09EC21C4 1 09EC2244 1 09EC22C4 1 09EC2344 1 09EC23C4 1 09EC2444 1 09EC24C4 1 09EC2544 1 09EC25C4 1 09EC2644 1 09EC26C4 1 09EC2744 1 09EC27C4 1 09EC2844 1 09EC28C4 1 09EC2944 1 09EC29C4 1 09EC2A44 1 09EC2AC4 1 09EC2B44 1 09EC2BC4 1 09EC2C44 1 09EC2CC4 1 09EC2D44 1 09EC2DC4 1 09EC2E44 1 09EC2EC4 1 09EC2F44 1 09EC2FC4 1 963EF008 1 963EF048 1 963EF088 1 963EF0C8 1 963EF108 1 963EF148 1 963EF188 1 963EF1C8 1 963EF208 1 963EF248 1 963EF288 1 963EF2C8 1 963EF308 1 963EF348 1 963EF388 1 963EF3C8 1 963EF408 1 963EF448 1 963EF488 1 963EF4C8 1 963EF508 1 963EF548 1 963EF588 1 963EF5C8 1 963EF608 1 963EF648 1 963EF688 1 963EF6C8 1 963EF708 1 963EF748 1 963EF788 1 963EF7C8 1 4C9C9808 1 4C9C9848 1 4C9C9888 1 4C9C98C8 1 4C9C9908 1 4C9C9948 1 4C9C9988 1 4C9C99C8 1 4C9C9A08 1 4C9C9A48 1 4C9C9A88 1 4C9C9AC8 1 4C9C9B08 1 4C9C9B48 1 4C9C9B88 1 4C9C9BC8 1 4C9C9C08 1 4C9C9C48 1 4C9C9C88 1 4C9C9CC8 1 4C9C9D08 1 4C9C9D48 1 4C9C9D88 1 4C9C9DC8 1 4C9C9E08 1 4C9C9E48 1 4C9C9E88 1 4C9C9EC8 1 4C9C9F08 1 4C9C9F48 1 4C9C9F88 1 4C9C9FC8 1 3B2E0010 1 3B2E0090 1 3B2E0110 1 3B2E0190 1 3B2E0210 1 3B2E0290 1 3B2E0310 1 3B2E0390 1 3B2E0410 1 3B2E0490 1 3B2E0510 1 3B2E0590 1 3B2E0610 1 3B2E0690 1 3B2E0710 1 3B2E0790 1 3B2E0810 1 3B2E0890 1 3B2E0910 1 3B2E0990 1 3B2E0A10 1 3B2E0A90 1 3B2E0B10 1 3B2E0B90 1 3B2E0C10 1 3B2E0C90 1 3B2E0D10 1 3B2E0D90 1 3B2E0E10 1 3B2E0E90 1 3B2E0F10 1 3B2E0F90 1 08BD6010 1 08BD6090 1 08BD6110 1 08BD6190 1 08BD6210 1 08BD6290 1 08BD6310 1 08BD6390 1 08BD6410 1 08BD6490 1 08BD6510 1 08BD6590 1 08BD6610 1 08BD6690 1 08BD6710 1 08BD6790 1 08BD6810 1 08BD6890 1 08BD6910 1 08BD6990 1 08BD6A10 1 08BD6A90 1 08BD6B10 1 08BD6B90 1 08BD6C10 1 08BD6C90 1 08BD6D10 1 08BD6D90 1 08BD6E10 1 08BD6E90 1 08BD6F10 1 08BD6F90 1 1863D020 1 1863D0A0 1 1863D120 1 1863D1A0 1 1863D220 1 1863D2A0 1 1863D320 1 1863D3A0 1 1863D420 1 1863D4A0 1 1863D520 1 1863D5A0 1 1863D620 1 1863D6A0 1 1863D720 1 1863D7A0 1 1863D820 1 1863D8A0 1 1863D920 1 1863D9A0 1 1863DA20 1 1863DAA0 1 1863DB20 1 1863DBA0 1 1863DC20 1 1863DCA0 1 1863DD20 1 1863DDA0 1 1863DE20 1 1863DEA0 1 1863DF20 1 1863DFA0 1 D6423060 1 D64230E0 1 D6423160 1 D64231E0 1 D6423260 1 D64232E0 1 D6423360 1 D64233E0 1 D6423460 1 D64234E0 1 D6423560 1 D64235E0 1 D6423660 1 D64236E0 1 D6423760 1 D64237E0 1 D6423860 1 D64238E0 1 D6423960 1 D64239E0 1 D6423A60 1 D6423AE0 1 D6423B60 1 D6423BE0 1 D6423C60 1 D6423CE0 1 D6423D60 1 D6423DE0 1 D6423E60 1 D6423EE0 1 D6423F60 1 D6423FE0
output
CACHE PARAMETERS Number of sets: 256 Associativity: 1 Cache line size: 64 Replacement policy: 1-bit LRU CACHE STATISTICS Total number of cache accesses: 512 Number of cache reads: 256 Number of cache writes: 256 Number of invalidates: 0 Number of cache hits: 128 Number of cache misses: 384 Cache hit ratio: 25.00% Cache miss ratio: 75.00% Number of evictions: 192 Number of writebacks: 64
one bit LRU policy output
2. Cache Parameters: Your model should support the following cache parameters to be configurable: num sets * num ways (associativity) * line size (in bytes) replacement_policy To simplify the implementation, you should assume that num sets, num ways and line size are always powers of 2, maximum value of num ways is 8 and line size ranges from 32 to 128 The modeled cache should support the following two replacement policies: (i) True LRU (replacement policy - 0), and (ii) 1-bit LRU (replacement policy-1). When a new cache line is brought into a set, it should first look to occupy an invalid cache block in that set. If there is no invalid block, then the replacement policy should choose the appropriate block as victim to make room for the new line. The details of the true LRU and 1-bit LRU replacement policies were discussed in class and are included in the lecture slides (ece585_lec9.pdf) As far as writes are concerned, you should assume a write-back cache with a write-allocate policy. You don't need to implement any timing details (such as hit time, miss penalty etc.) for the cache 3. Simulator output: After the last access in the trace has been simulated, the simulator should output the following statistics Total number of cache accesses Number of cache reads Number of cache writes Number of invalidates Number of cache hits Number of cache misses Cache hit ratio Cache miss ratio Number of evictions Number of writebacks 4. Poject Evaluation: Once you have understood all the above details, you are ready to implement the simulator. In week 9 of classes, you'll be provided a set of input traces which will be used to evaluate your project submissions. In the meantime, you can develop your own short test traces (following the trace format described above) to validate the correctness of your simulator. A major portion of your project grade will be based on the accuracy of your simulator output for the evaluated traces. You'll be required to include your simulator results in the final report. Simulator Components Trace Reader Reads the input trace and passes the address and access type information to the cache model Cache Model Models the workings of the cache Does the access hit in the cache? If it is a miss, does a block need to be evicted from the cache? If an eviction is needed, which block should be evicted? Need to keep track of each way in each set (valid, dirty, tag) Output Generator Keeps track of all the relevant cache statistics (hits, misses, writebacks etc.) Once the simulation has completed, print the statistics Objective Develop a simulator which models a single level of cache Programming Language Any high-level programming language (C, C++, JAVA etc. Simulator Inputs Address trace provided by the instructor Cache parameters (cache line size, number of sets, associativity, replacement policy) Simulator Output Cache statistics (hit ratio, read traffic, write traffic) etc. Proiect Obiective The goal of the project is to simulate a single level of cache in software. You will write your own simulator in a software platform of your own choice (such as C, C++, JAVA, VHDL, Verilog etc.). The simulator will take the provided input address trace as its input. It will implement the workings of the cache. Specifically, it will keep track of which blocks are brought into the cache and which blocks are being evicted. At the completion of the trace, the simulator will provide statistics about cache hit ratio, read traffic, write traffic etc Note that there is no need to model the actual data stored in the cache. The input trace contains information only about the addresses that are being accessed. Since there is no data information in the trace, there is no way to model the data contents any way Proiect Details Please read the following details carefully and follow them, when implementing your simulator 1. Input trace: The simulator will take an address trace as its input. This trace captures the sequence of accesses that are being made to the cache. For each access, the trace provides the type of access and the memory address that is being accessed. Each line in the trace has the following format: Access type Hex Address Access_type signifies the type of the memory operation (read, write or invalidate). It is encoded as follows: Access type 0 indicates a read. Access type-1 indicates a write and Access type 2 indicates an invalidate operation. Hex address is the address which is being accessed. It is encoded in the hexadecimal format Each address is a 32-bit number (8 hexadecimal digits) and signifies the byte which is being accessed The two fields in each line are separated by a whitespace Example l: Let us assume that the first line in the address trace is as follows 0 00A53C00 This represents a read request to the byte address 0x00A53C00 Example 2: Consider another line in the address trace 1 3C44DB20 This represents a write request to the byte address 0x3C44DB20 Example 3: Another line in the address trace is as follows 2 00A53C04 This represents an invalidation request for address 0x00A53C04. If the cache line that contains address 00A53C04 is present in the cache, then it should be evicted from the cache and its valid bit should be reset to 0. If the invalidated address is not present in the cache, then nothing needs to be done 2. Cache Parameters: Your model should support the following cache parameters to be configurable: num sets * num ways (associativity) * line size (in bytes) replacement_policy To simplify the implementation, you should assume that num sets, num ways and line size are always powers of 2, maximum value of num ways is 8 and line size ranges from 32 to 128 The modeled cache should support the following two replacement policies: (i) True LRU (replacement policy - 0), and (ii) 1-bit LRU (replacement policy-1). When a new cache line is brought into a set, it should first look to occupy an invalid cache block in that set. If there is no invalid block, then the replacement policy should choose the appropriate block as victim to make room for the new line. The details of the true LRU and 1-bit LRU replacement policies were discussed in class and are included in the lecture slides (ece585_lec9.pdf) As far as writes are concerned, you should assume a write-back cache with a write-allocate policy. You don't need to implement any timing details (such as hit time, miss penalty etc.) for the cache 3. Simulator output: After the last access in the trace has been simulated, the simulator should output the following statistics Total number of cache accesses Number of cache reads Number of cache writes Number of invalidates Number of cache hits Number of cache misses Cache hit ratio Cache miss ratio Number of evictions Number of writebacks 4. Poject Evaluation: Once you have understood all the above details, you are ready to implement the simulator. In week 9 of classes, you'll be provided a set of input traces which will be used to evaluate your project submissions. In the meantime, you can develop your own short test traces (following the trace format described above) to validate the correctness of your simulator. A major portion of your project grade will be based on the accuracy of your simulator output for the evaluated traces. You'll be required to include your simulator results in the final report. Simulator Components Trace Reader Reads the input trace and passes the address and access type information to the cache model Cache Model Models the workings of the cache Does the access hit in the cache? If it is a miss, does a block need to be evicted from the cache? If an eviction is needed, which block should be evicted? Need to keep track of each way in each set (valid, dirty, tag) Output Generator Keeps track of all the relevant cache statistics (hits, misses, writebacks etc.) Once the simulation has completed, print the statistics Objective Develop a simulator which models a single level of cache Programming Language Any high-level programming language (C, C++, JAVA etc. Simulator Inputs Address trace provided by the instructor Cache parameters (cache line size, number of sets, associativity, replacement policy) Simulator Output Cache statistics (hit ratio, read traffic, write traffic) etc. Proiect Obiective The goal of the project is to simulate a single level of cache in software. You will write your own simulator in a software platform of your own choice (such as C, C++, JAVA, VHDL, Verilog etc.). The simulator will take the provided input address trace as its input. It will implement the workings of the cache. Specifically, it will keep track of which blocks are brought into the cache and which blocks are being evicted. At the completion of the trace, the simulator will provide statistics about cache hit ratio, read traffic, write traffic etc Note that there is no need to model the actual data stored in the cache. The input trace contains information only about the addresses that are being accessed. Since there is no data information in the trace, there is no way to model the data contents any way Proiect Details Please read the following details carefully and follow them, when implementing your simulator 1. Input trace: The simulator will take an address trace as its input. This trace captures the sequence of accesses that are being made to the cache. For each access, the trace provides the type of access and the memory address that is being accessed. Each line in the trace has the following format: Access type Hex Address Access_type signifies the type of the memory operation (read, write or invalidate). It is encoded as follows: Access type 0 indicates a read. Access type-1 indicates a write and Access type 2 indicates an invalidate operation. Hex address is the address which is being accessed. It is encoded in the hexadecimal format Each address is a 32-bit number (8 hexadecimal digits) and signifies the byte which is being accessed The two fields in each line are separated by a whitespace Example l: Let us assume that the first line in the address trace is as follows 0 00A53C00 This represents a read request to the byte address 0x00A53C00 Example 2: Consider another line in the address trace 1 3C44DB20 This represents a write request to the byte address 0x3C44DB20 Example 3: Another line in the address trace is as follows 2 00A53C04 This represents an invalidation request for address 0x00A53C04. If the cache line that contains address 00A53C04 is present in the cache, then it should be evicted from the cache and its valid bit should be reset to 0. If the invalidated address is not present in the cache, then nothing needs to be done
