kindly solve

with explanation and calculation

Consider a 5 staged pipelined MIPS processor where its operation is divided into 5 stages. Each stage is timed as shown below. What is the clock period of this processor. Execution Time Stage: Fetch Decode Execute Memory WriteBack Time: 138 ns 181 ns 363ns. 307ns73ns a. 73.00ms b. 363.00 ns c. 212.40ns d. 1062.00 ns e. None of the options