KNOWN: Geometry of pin fin array used as heat sink for a computer chip. Array convection and chip substrate conditions. FIND: Effect of pln diameter, spacing and length on maximum allowable chip power dissipation. SCHEMATIC: Physical System: Copper (k = 400 Wim K) Pins (N). DELP 60=20 C 250 W/m2K ho LILLO T = 75C, 4c Ac = (0.0127 m2 1,04 ME 10W RY f.c - Lo = 0.005 m kb - 1 WmK = 20 C h 40 W/m2K Thermal Circuit: 9; 11, Ac Ac R.CACT RO 47 ac ASSUMPTIONS: (1) Steady-state conditions, (2) One-dimensional heat transfer in chip-board is umbily, (3) Negligible pin chip contact resistance, (1) Constant properties, (6) Negligible chip thermal resistance (6) Uniform chip temperature. ANALYSIS: The bestal jxwer dissipation is = 9;+ where Some relevant formulas: The resistance of the pin array is R4,0 =(174) where NAC (1-11) o = 1 T AL A = NAF + Ap AF = DL. = D. (1,+D/4) Draw the pin diameter Dp vs ggraph for N=16, 25, 36 (where 0.5