Lab 4 Part 4: Stopwatch Design This project is to design a stopwatch in VHDL by using the hierarchical design approach shown in the figure below. I start+ I stop+ clk reset g2 g1 en en en start stop fsm clkin clkout clkdiv clk2 clk reset g3 watch g4 y1[3:0] y1[3:0] A din[3:0] dout[6:0] sevensegdec f1[6:0] clk2 clk y0[3:0] y0[3:0] reset Dand din[3:0] dout[6:0] sevensegdec g5 ang Figure 1. Stopwatch block diagram f2[6:0] Pang The top-level I/O ports used in this design are shown below. Port Names Port Direction Port Size start stop Input 1 Input 1 clk Input 1 reset Input 1 fl Output fo Output 7 7 Prof. The stopwatch design has the following features: 1). The frequency of the input "clk" signal is 50 MHz. 2). At any time, if the "reset" input is logic high, the outputs of the stopwatch will be zeros. 3). When the "start" input is logic high, the stopwatch will start counting. 4). When the "stop" input is logic high, the stopwatch will stop, but the stopwatch output will maintain its value. After that, when the "start" input is logic high again, the stopwatch will resume counting from its old value. 5). Each of the internal signals y1 and y0 is a 4-bit binary number with a range from 0 to 9. Assuming y1 = (0101) 2 = 5, y0 = (0111) 2 = 7, this means 57 seconds. If you press the "stop" button, the stopwatch will stop at 57 seconds and keep the value unchanged. After pressing the "start" button, the stopwatch will continue counting every second until y1 = (1001) 2 ng 9, yo (1001) 2 9, which means 99 seconds. After 99 seconds, the stopwatch will return to 0 and then increase its value every second. sevensegdec represents the seven-segment decoder design. The stopwatch data should be displayed on two seven-segment decoder devices. Demo Requirement: You need to download your design into the FPGA board and show a demo to your lab instructor. Note: You can use the PIN_P11 as your clk input pin.