Lab2.pdf-TeXworks File Edit Sech View Typeset Scripts Window Help This lab introduces you to finite state machine design. The lab will take the "ALU" module from the previous lab (lab 1) and inject a sequence of commands into the design. To complete this lab, you will need to design a state machine module, and a test bench. Lab 2 State Machine Lab 1 Outvjst Test bench reset lAsynch Figure 1. Lab 2 Design: NOTE that a working lab 1 is now provided to you Lab 1 Wrapper: The Labl module has 5 inputs; cik, reset, en, A, and sel. The ALU performs an instruction operation based on the sel input and when en is asserted State Machine: The state machine module has 5 inputs; clk, reset, sm_en, and cmd id. Outputs en and sel are connected to the Lab1 module. The state machine asynchronously checks if the reset input is set to '1'. If it is set to '1', it transitions to the initial state. If the value of reset is '0', and on the rising edge of clk, it checks for the sm_en input. If the value of sm_en is '1' then the state machine starts, otherwise it remains at its initial state. The sm_en should remain high for 1 clock period for it to work since it is synchronous to the clock. When sm_en is set, whatever is on cmd_id is to be captured in a 15-bit register that will output cmd_id r. When a smen '1' is received, the state machine transitions to the S1 state if a valid ALU instruction is to be executed This is shown in Figure 2. sm en must be de-asserted after one cycle by the test bench. The registered cmd id r is to be used by the state machine to transition from S1 state and onwards Lab2.pdf-TeXworks File Edit Sech View Typeset Scripts Window Help This lab introduces you to finite state machine design. The lab will take the "ALU" module from the previous lab (lab 1) and inject a sequence of commands into the design. To complete this lab, you will need to design a state machine module, and a test bench. Lab 2 State Machine Lab 1 Outvjst Test bench reset lAsynch Figure 1. Lab 2 Design: NOTE that a working lab 1 is now provided to you Lab 1 Wrapper: The Labl module has 5 inputs; cik, reset, en, A, and sel. The ALU performs an instruction operation based on the sel input and when en is asserted State Machine: The state machine module has 5 inputs; clk, reset, sm_en, and cmd id. Outputs en and sel are connected to the Lab1 module. The state machine asynchronously checks if the reset input is set to '1'. If it is set to '1', it transitions to the initial state. If the value of reset is '0', and on the rising edge of clk, it checks for the sm_en input. If the value of sm_en is '1' then the state machine starts, otherwise it remains at its initial state. The sm_en should remain high for 1 clock period for it to work since it is synchronous to the clock. When sm_en is set, whatever is on cmd_id is to be captured in a 15-bit register that will output cmd_id r. When a smen '1' is received, the state machine transitions to the S1 state if a valid ALU instruction is to be executed This is shown in Figure 2. sm en must be de-asserted after one cycle by the test bench. The registered cmd id r is to be used by the state machine to transition from S1 state and onwards
