Layout the gate masks used to fabricate Intels 14nm 6transistor SRAM. (hint need to find intel 14nm SRAM layout on web).

OR

Layout the gate mask used to fabricate Intels 22nm 6-transistor 3 SRAM cells.

Only required to do the layout of the gate masks for intels 14 or 22nm SRAM but not both.

Assume mask and printed feature are of ratio 1:1. Draw and label feature sizes to scale.

Can you come up with a technique to pattern two different transistor gate dimension (commonly needed in designs)?