Layout & Transistor Capacitors.

For the following layout, assume C_ox = 7fF/um², C_ov = 1fF/um, C_j = 1fF/um², C_jsw = 0.01fF/um, C_cb = 1fF/um^₂. The dimensions are given in units, where =0.5m. Assume all poly gates have L=1m and L_D=0.05m. a) Draw the equivalent circuit. Combine all parallel transistors.

b) Assume that V_O=0.5V, V_X=0.4V, V_Y=0V, V_G1=1V, V_G2=1.5V. Also, assume that the p-substrate is grounded, V_T0=0.7V, and =0. What region are the transistors operating in? c) Calculate the total gate capacitance of the transistors. d) Calculate the total junction capacitance at nodes O, X, and Y. Note for the perimeter terms.

Hint: You need a channel-bulk capacitance. Use C_jcb=1fF/um².

P-sub Poly 10 P-sub Poly 10