Listing $10\mathrm{.}9$ Verilog Description of the Eightbit Parallel In$/$Parallel Out Shift

Register for Multiplication and Division Operations

module PIPO$\_$shift$\_$register$($number$,$p$2,$md$,$clk$,$result,ovr$)$ ;

input $7$:$0$ number;

input $[1$:$0]p2$;

input md$,$ clk;

output reg $7$:$0$ result;

output reg ovr;

initial ovr $=1^{\text{'}}b0$;

always@$($posedge clk$)$

begin

if $)$

$\{$ovr$,$ result