Logic styles and power

In this problem, you need to implement a 6-input AND gate. All the gates in your design are from the library below containing the cell types, together with their properties in terms of capacitance.

Inv NOR2 NOR3 NAND2 NAND3 NAND6

Cin 48 fF 48 fF 48 fF 48 fF 48 fF 48 fF

Cout 85 fF 101 fF 117 fF 105 fF 132 fF 200fF

Assume that all the circuits you will implement operate at a supply voltage of 3V and a clock frequency of 20MHz. All the six primary inputs of the AND gate have an equal probability of being 0 and 1. You can ignore the power dissipated by the input signals.

a. First, implement the 6-input AND using a 6-input NAND and an inverter. Determine the average power dissipation (Pav) of this implementation.

b. Implement the same function using predominantly 3-input NANDs (plus some other necessary gates). Draw the schematic of your design and determine Pav.

c. Assume now that the design of part b is laid out with dynamic gates instead. Assume that this reduces all the capacitances with a factor of 2. All gates however have an additional clock input with a capacitance equal to 20fF. The dynamic gates are cascaded using static CMOS inverter in between (i.e., domino logic). Draw the schematic and determine Pav.