Loop: l.d f2,0 (rl) add.d f4,f2,f0 1.d f6,0 (r2) add.d 6,f4, f6 1.d f8,0 (r3) add.d f10, f8, f6 s.d f10,0 (r2) addi addi addi bnez r3,r3,-8 r2,r2,-8 rl,rl,-8 rl,Loojp medskip oindent Use a MIPS pipeline extended with a two-issue Tomasulo's algorithm with speculation Assume two instructions can be issued on every clock cycle, even if they are dependent except when both are floating point operations. Branches are single-issue. Assume one integer functional unit is used for both ALU operations and effective address calculations. Assume that a separate non-pipelined FP functional unit for each operation type. Assume that there is dynamic branch prediction hardware and a separate functional unit to evaluate branch predictions/conditions. Assume that branches single issue. Assue there are two CDBs Assume that Issue and Write take 1 clock cycle. Integer operations take one cycle in their execution unit, and FP additions take 3 cycles in theirs F?II in the timing chart for 2 iterations of the loop . Loop: l.d f2,0 (rl) add.d f4,f2,f0 1.d f6,0 (r2) add.d 6,f4, f6 1.d f8,0 (r3) add.d f10, f8, f6 s.d f10,0 (r2) addi addi addi bnez r3,r3,-8 r2,r2,-8 rl,rl,-8 rl,Loojp medskip oindent Use a MIPS pipeline extended with a two-issue Tomasulo's algorithm with speculation Assume two instructions can be issued on every clock cycle, even if they are dependent except when both are floating point operations. Branches are single-issue. Assume one integer functional unit is used for both ALU operations and effective address calculations. Assume that a separate non-pipelined FP functional unit for each operation type. Assume that there is dynamic branch prediction hardware and a separate functional unit to evaluate branch predictions/conditions. Assume that branches single issue. Assue there are two CDBs Assume that Issue and Write take 1 clock cycle. Integer operations take one cycle in their execution unit, and FP additions take 3 cycles in theirs F?II in the timing chart for 2 iterations of the loop