Loop: load.d f2, 0(r1)

mul.d f6, f4, f2

add.d f8, f8, f2

store.d f8, 0(r2)

addi r2, r2, # -8

addi r1, r1, # -8

bnez r1, Loop

Assume a MIPS 5-stage pipeline for ALU operations. Assume that there is a fp multiplier and a fp adder that are fully pipelined with depths 7 and 4 stages respectively (the ALU unit has depth 1 stage). Assume full forwarding (and in-order issue, in-order execution). Assume the branch is handled by predicting not taken and all structural hazards are handled in the ID stage.