The Logic Diagram and Truth Table indicate the functional characteristics of the '195 4-bit shift register. The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The '195 has two primary modes of operation, shift right (QoQ) and parallel load, which are controlled by the state of the Parallel Enable (PE) input. When the PE input is HIGH, serial data enters the first flip-flop Qo via the J and K inputs and is shifted one bit in the direction QoQ Q2 Q3 following each LOW-to-HIGH clock transition. The JK inputs provide the flexibility of the JK type input for special applications, and the simple D type input for general applications by tying the two pins together. When the PE input is LOW, the '195 appears as four common clocked D flip-flops. The data on the parallel inputs Po, P1, P2, P3 is transferred to the respective Qo. Q1, Q2, Q3 outputs following the LOW-to-HIGH clock transition. Shift left operation (Q3 Q2) can be achieved by tying the Qn outputs to the Pn - 1 inputs and holding the PE input LOW. All serial and parallel data transfers are synchronous, occuring after each LOW-to-HIGH clock transition. Since the '195 utilizes edge-triggering, there is no restriction on the activity of the J, K, Pn and PE inputs for logic operation except for the setup and release time requirements. A LOW on the asynchronous Master Reset (MR) input sets all Q outputs LOW, independent any other input condition. OPERATING MODES Asynchronous Reset Shift, Set First Stage Shift, Reset First Stage Shift, Toggle First Stage Shift, Retain First Stage PE J K Po R CD o -CCP S Qo 8 MODE SELECT TABLE INPUTS Qo MR PE J K L X X X X H H H H h SEEK PL h h h 1 Parallel Load HI X X Pn Po P1 H = HIGH Voltage Level L= LOW Voltage Level X = Immaterial 1= LOW voltage level one setup time prior to the LOW to HIGH clock transition. h = HIGH voltage level one setup time prior to the LOW to HIGH clock transition. Pn (qn) = Lower case letters indicate the state of the referenced input for output) one setup time prior to the LOW to HIGH clock transition. h 1 - A I 1 LOGIC DIAGRAM OUTPUTS Pn Qo Q1 Q2 Q3 Q3 L L L L X H L S ar x xxxx 01 90 91 92 90 91 92 90 90 q1 90 qo q1 P A - CP S 0 Q 92 92 P3 A I 2 p2 p3 P3 H S 92 92 q2 92 MA CP CD 03 03 Q303 CONNECTION DIAGRAM PINOUT A MR K 3 Po 4 P5 P2 6 P3 GND 8 16 Vcc 15 Qo 14 Q 13 Q2 12 Q3 Q3 10 CP 9 PE