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lw $t0, 0 ($s0) add $t0, $s0, $t0 addi $t0, $t0, 16 lw $t1, 0 ($t0) Assuming the processor has full forwarding, but also the
lw $t0, 0 ($s0)
add $t0, $s0, $t0
addi $t0, $t0, 16
lw $t1, 0 ($t0)
Assuming the processor has full forwarding, but also the instruction and data memory is not separated, populate the following pipeline diagram using compactnotation (Use S for stalls)
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