Many SMP (Symmetric multiprocessing) systems have different level of caches; one level is local to each processing core, and another level is shared among all processing cores. Answer the following questions in this regard: a) Redraw the figure given below to demonstrate the architecture of this multi-level cache system. b) Explain why are caching systems are designed in this way? c) Explain with the help of an example what does cache coherence means in this architecture d) Can a SMP system can guarantee that performance will always be better than a uniprocessor system. Yes or No and then justify your claim. CPU registers cache CPU registers cache memory CPU registers cache