Master-Slave Flip-Flop While a transparent latch may be desirable in some situations, it is not always useful. Often one would like to take a "snapshot" of the input signal: that is store the value present on the input at an instant of time. Such a device is called a flip-flop. Flip-flops have no period when they are transparent. A latch is said to be "level-triggered", meaning the device is active while the entire time the gate is asserted. Flipflops, on the other hand, are said to be edge-triggered: the state of the flip-flop changes only during the infinitesimal period the Strobe input transitions from negated to asserted. One of the simplest ways to construct an edge-triggered flip-flop is to use two identical transparent latches wired in a master-slave configuration: The main difference is latches are level-triggered, using an input called "Gate"; while flip-flops are edge triggered, using an input called "Strobe". The latch on the left (the Master) is transparent while Strobe is LOW (due to the inverter), and its output is free to follow the Data input. However, the latch on the right (the slave) is not transparent when Gate is LOW, so the changes on the master's output will not be passed on. When Strobe transitions from LOW to HIGH (a rising edge), the situation reverses: the Master in no longer transparent, so it retains its last value. Meanwhile, the slave becomes transparent, allowing the master's output through. Although the slave is now transparent, its data input (the master's output) will not change because the master is not transparent. When Strobe falls (transitions from HIGH to LOW) the slave becomes non-transparent, retaining its last value (which was the master's output at the last rising edge). The Master is now transparent, and its output is free to follow the Data input, but since the slave is not transparent, the final output will not be affected. The upshot of all this is: the flip-flop's output will change only when Strobe rises. There is never a period of transparency from Data input to final output. A rising edge triggered flip-flop! MasterSlave.vhd: which instantiates two TransLatch components to create a VHDL description of the master-slave flip-flop as a component named MasterSlave. TestMasterSlave.vhd: a "test stub" which instantiates the MasterSlave component and provides it with input and output signals