Match the term in the first column with its correct description in the second column. 1. The processor can't execute an instruction in the proper clock cycle because a needed resource is busy. 2. 3. Forwarding unit 4 Temporal locality Responsible for solving most data hazards by bypassing the missing data from pipeline registers. A cache structure in which a block can be placed in any location in the cache. Items accessed recently are likely to be accessed again soon; like instructions in loops. Items near those accessed recently are likely to be accessed soon; like arrays data. The address maps to a unique block in cache; (Block address) modulo (#Blocks in cache). Next instruction is fetched before the previous one completes its execution (overlapping). 5. Spatial locality 6. Hazard detection unit 7. Pipelining 8. Responsible for solving a load-use data hazard. N-way set associative cache Fully associative cache 10. Control (Branch hazard 9. Responsible for stalling the pipeline in a load-use data hazard. The address maps to a unique set in cache; (Block address) modulo (# Sets in cache). 11. The processor is not clear about what the next instruction to fetch is. 12. Shows the details of what is happening within the pipeline during each clock cycle. Shows what is happening within the pipeline during ALL clock cycles. Structural hazard Multi clock cycle pipeline diagram 13. A method of solving a control hazard by assuming a given outcome for the branch. 14. 15. A hazard arises from the dependence of one instruction on an earlier one that is still in the pipeline