MHz $6670$MHz $15000$MHz $1300$ OMHz $770$ OThe maximum frequency at which a Multicycle design would run at is nearlyGHz $2\mathrm{.}5$ OGHz $3\mathrm{.}3$ OGHz $5\mathrm{.}00$GHz $1\mathrm{.}3$ Ops $13000$ps $1100$ Ops $1200$:Assume the following operation times for different MIPS datapath componentsInstruction memory: $400$ ps$,$ Data memory: $400$ ps$,$ ALU: $300$ ps$,$ Read or Write to Register File: $200$ psAssume the following instruction mix: $30\%$ ALU, $30\%$ Loads, $20\%$ stores, $20\%$ branchesThe maximum frequency at which a Single Cycle design would run at is nearlyThe time it takes to complete the execution of a store operation in Multicycle design is aboutps $1500$ OThe average CPI of the multi$-$cycle MIPS is about$4\mathrm{.}104\mathrm{.}003\mathrm{.}8$