microcontroller 8051 (MPC82G516A) to finish square wave generation. (timer)

question fig.

microcontroller 8051 (MPC82G516A) to finish square wave generation.

some code picture

number is 10626140

timer0 is 1062fz

timer1 is 6140hz (use mode2)

timer1 mode2 need TL0&TH0&TL1&TH1

MPC82G516A timer information

Square Wave Generator: Using your kit write a C program to generate 2 square waves on P1.0 and P1.1 simultaneously using timer. The frequencies should be according to your numberID as follows: P1.0) Left 4 digits of your number ID will be frequency in Hz P1.1) Right 4 digits of your number ID will be frequency in Hz For example, if your Student ID is 10626140 then P1.0 should generate square wave with frequency of 1062 Hz and P1.1 should have frequency of 6140 Hz. Output Signal: The output signal general waveform is shown in following figure: P1.0 PLOS VEH T= 1/f 5 0 50% 50% 50% The duty cycle of the output is 50% so you can simply calculate half a period and complement the output pin in each T/2 time. Project Bts Project: 01 Target 1 a Source Group 1 STARTUP A51 main.c main.c D STARTUP.A51 #include "REG MPC82G516.H void timero () interrupt 1 using 2 3 TRO=0; TLON THO= TRO=1; P10=-P10; timero ooo en SEE 10 } 11 void timerl ( interrupt 3 using 12 El 13 Pll=-P11; 14 L 15 main() 16 C TRO=0; TRI=0; TF0=0; TF1=0; TMOD=0X21; TLO= THO= TL1= TH= ETO=1; ET1=1; EA=1; TRO=1; TRI=1; while (1): mode2 L 11 Timers/Counters The MPC82G516A has three 16-bit Timer/Counters: Timer O, Timer 1 and Timer 2. Each consists of two 8-bit registers, THX and TLX (where, x= 0, 1, or 2). All of them can be configured to operate either as timers or event counters. In the Timer function, the TLX register is incremented every 12-clock cycle or 1-clock cycle, which is selectable by software. Thus one can think of it as counting clock cycles. When counting every 12 clock cycles, the count rate is 1/12 of the oscillator frequency In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin- TO, T1, or T2. In this function, the external input is sampled every clock cycle for TO pin and T1 pin, and 12-clock cycle for T2 pin. When the samples show a high and then a low, the count is incremented. The new count value appears in the register when the transition was detected. For Timer 0 and Timer 1, it takes 2 clock cycles to recognize a 1-to-0 transition, the maximum count rate is 1/2 of the oscillator frequency; for Timer 2, it takes 24 clock cycles to recognize a 1-to-o transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one clock cycle for Timer 0 and Timer 1, and 12- clock cycles for Timer 2.4 For Timer O and Timer 2, in addition to their standard 8051's timer function, some special new functions are added in. The following sub-sections will describe these timer/counters in detail. 11.1 Timer 0 and Timer 14 The Timer or Counter function is selected by control bits C/-T in the Special Function Register TMOD, as shown below. These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1, MO) in TMOD. Mode 0, 1 and 2 are the same for these two Timer/Counters. Mode 3 is different. In addition to TMOD, another Special Function Registers TCON and AUXR2 contains several control bits and status flags related to these two Timers, as also shown below. TMOD (Address=89H, Timer/Counter Mode Control Register, Reset Value=0000,0000B) Timer 12 Timer 02 716152T 4T3 T2T1T02 GATE CAT M1 MO GATE CAT M1 MO | GATE: Gating control when set. Timer/Counter 0 or 1 is enabled only while /INTO or /INT1 pin is high and TRO or TR1 control pin is set. When cleared, Timer 0 or 1 is enabled whenever TRO or TR1 control bit is set. C/-T: Timer or Counter Selector. Clear for Timer operation (input from internal system clock). Set for Counter operation (input from TO or T1 input pin). M1 MO Operating Mode 0 0 8-bit Timer/Counter. THX with TLx as 5-bit prescaler. 0 1 16-bit Timer/Counter. THx and TLx are cascaded; there is no prescaler. 10 8-bit auto-reload Timer/Counter. THX holds a value which is to be reloaded into TLX each time it overflows. 1 1 (Timer O) TLO is an 8-bit Timer/Counter controlled by the standard Timer O control bits. THO is an 8-bit timer only controlled by Timer 1 control bits. 1 1 (Timer 1) Timer/Counter stopped. L LL- 11.1.2 Mode 1: 16-Bit Timer/Counter Mode 1 is the same as Mode 0, except that the Timer register uses all 16 bits. Refer to Figure 11-2. In this mode, THx and TLx are cascaded, there is no prescalere TCON (Address=88H, Timer/Counter Control Register, Reset Value=0000,0000B 7 6 5 4 3 2 1 0 TF1 TR1 TF02| TRO IE1e| Te IE02| ITO TF1: Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by....Idware when processor vectors to interrupt routine. TR1: Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off. TFO: Timer O overflow Flag. Set by hardware on Timer/Counter 0 overflow. Cleared by hardware when processor vectors to interrupt routine. TRO: Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off. Figure 11-2. Timer 1 in Mode 1: 16-Bit Timer/Counter Lt 1 1 LL L Fosc +12+ +12 Att Overflow AUXR2 (Address=A6H, Auxiliary Register2, Reset Value=0000,0000B) 7 6 5 4 3 2 1 1 0 TOX12 T1X12 URMOX6 S2TRS2SMOD S2TX12S2CKOE TOCKOE e topt TL1 1 (8 Bits) TH12 (8 Bits) TF14 Timer 1 Interrupte T1X12 T1 Pin die CAT 1 TR1 TOX12: Timer O clock source select while C/-T=0. Set to select Fosc as the clock source, and clear to select Fosc/12 as the clock source. T1X12: Timer 1 clock source select while C/-T=0. Set to select Fosc as the clock source, and clear to select Fosc/12 as the clock source. TOCKOE: Set/clear to enable/disable Timer O clock-out function from P3.4.- L -GATE L /INT1 pine The four operating modes are described in the following text. L * Fosc is the system clock 11.1.1 Mode 0: 13-Bit Timer/Counter L 11.1.3 Mode 2: 8-Bit Auto-Reload L Timer 0 and Timer 1 in Mode 0 look like an 8-bit Counter with a divide-by-32 prescaler. And, Mode 0 operation is the same for these two timers. Figure 11-1 shows the Mode 0 operation. In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all Os, it sets the Timer interrupt flag TFx. The counted input is enabled to the Timer when TRX=1 and either GATE=0 or /INTx=1. (Setting GATE=1 allows the Timer to be controlled by external input /INTx, to facilitate pulse width measurements). TRX and TFX are control bits in SFR TCON. The GATE bit is in TMOD. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3). Mode 2 configures the Timer register as an 8-bit Counter (TLx) with automatic reload, as shown in Figure 11-3. Overflow from TLX not only sets TFx, but also reloads TLX with the contents of THx, which is preset by software. The reload leaves THX unchanged. Figure 11-3. Timer 1 in Mode 2: 8-Bit Auto-Reload The 13-bit register consists of all 8 bits of THx and the lower 5 bits of TLx. The upper 3 bits of TLx are indeterminate and should be ignored. Setting the run flag (TRX) does not clear these registers. That is to say the user should initialize THX an TLx before start counting L LLLL1 L L L Figure 11-1. Timer 1 in Mode 0: 13-Bit Timer/Counter Overflow TL1 (8 Bits) TF1CH Timer 1 Interrupte T1X124 Fosc +124 T1 Pin I cite L TR14 TL TH1 Overflow (5 Bitsy (8 Bits) - TF1+ Timer 1 Interrupte TH1e (8 Bits) GATE ortopot dt GATED T1X12 T1 Pin L /INT1 pin CAT TR14 * Fosc is the system clock GATE o r LLLLLLL L INTO pine /INT1 pine Square Wave Generator: Using your kit write a C program to generate 2 square waves on P1.0 and P1.1 simultaneously using timer. The frequencies should be according to your numberID as follows: P1.0) Left 4 digits of your number ID will be frequency in Hz P1.1) Right 4 digits of your number ID will be frequency in Hz For example, if your Student ID is 10626140 then P1.0 should generate square wave with frequency of 1062 Hz and P1.1 should have frequency of 6140 Hz. Output Signal: The output signal general waveform is shown in following figure: P1.0 PLOS VEH T= 1/f 5 0 50% 50% 50% The duty cycle of the output is 50% so you can simply calculate half a period and complement the output pin in each T/2 time. Project Bts Project: 01 Target 1 a Source Group 1 STARTUP A51 main.c main.c D STARTUP.A51 #include "REG MPC82G516.H void timero () interrupt 1 using 2 3 TRO=0; TLON THO= TRO=1; P10=-P10; timero ooo en SEE 10 } 11 void timerl ( interrupt 3 using 12 El 13 Pll=-P11; 14 L 15 main() 16 C TRO=0; TRI=0; TF0=0; TF1=0; TMOD=0X21; TLO= THO= TL1= TH= ETO=1; ET1=1; EA=1; TRO=1; TRI=1; while (1): mode2 L 11 Timers/Counters The MPC82G516A has three 16-bit Timer/Counters: Timer O, Timer 1 and Timer 2. Each consists of two 8-bit registers, THX and TLX (where, x= 0, 1, or 2). All of them can be configured to operate either as timers or event counters. In the Timer function, the TLX register is incremented every 12-clock cycle or 1-clock cycle, which is selectable by software. Thus one can think of it as counting clock cycles. When counting every 12 clock cycles, the count rate is 1/12 of the oscillator frequency In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin- TO, T1, or T2. In this function, the external input is sampled every clock cycle for TO pin and T1 pin, and 12-clock cycle for T2 pin. When the samples show a high and then a low, the count is incremented. The new count value appears in the register when the transition was detected. For Timer 0 and Timer 1, it takes 2 clock cycles to recognize a 1-to-0 transition, the maximum count rate is 1/2 of the oscillator frequency; for Timer 2, it takes 24 clock cycles to recognize a 1-to-o transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one clock cycle for Timer 0 and Timer 1, and 12- clock cycles for Timer 2.4 For Timer O and Timer 2, in addition to their standard 8051's timer function, some special new functions are added in. The following sub-sections will describe these timer/counters in detail. 11.1 Timer 0 and Timer 14 The Timer or Counter function is selected by control bits C/-T in the Special Function Register TMOD, as shown below. These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1, MO) in TMOD. Mode 0, 1 and 2 are the same for these two Timer/Counters. Mode 3 is different. In addition to TMOD, another Special Function Registers TCON and AUXR2 contains several control bits and status flags related to these two Timers, as also shown below. TMOD (Address=89H, Timer/Counter Mode Control Register, Reset Value=0000,0000B) Timer 12 Timer 02 716152T 4T3 T2T1T02 GATE CAT M1 MO GATE CAT M1 MO | GATE: Gating control when set. Timer/Counter 0 or 1 is enabled only while /INTO or /INT1 pin is high and TRO or TR1 control pin is set. When cleared, Timer 0 or 1 is enabled whenever TRO or TR1 control bit is set. C/-T: Timer or Counter Selector. Clear for Timer operation (input from internal system clock). Set for Counter operation (input from TO or T1 input pin). M1 MO Operating Mode 0 0 8-bit Timer/Counter. THX with TLx as 5-bit prescaler. 0 1 16-bit Timer/Counter. THx and TLx are cascaded; there is no prescaler. 10 8-bit auto-reload Timer/Counter. THX holds a value which is to be reloaded into TLX each time it overflows. 1 1 (Timer O) TLO is an 8-bit Timer/Counter controlled by the standard Timer O control bits. THO is an 8-bit timer only controlled by Timer 1 control bits. 1 1 (Timer 1) Timer/Counter stopped. L LL- 11.1.2 Mode 1: 16-Bit Timer/Counter Mode 1 is the same as Mode 0, except that the Timer register uses all 16 bits. Refer to Figure 11-2. In this mode, THx and TLx are cascaded, there is no prescalere TCON (Address=88H, Timer/Counter Control Register, Reset Value=0000,0000B 7 6 5 4 3 2 1 0 TF1 TR1 TF02| TRO IE1e| Te IE02| ITO TF1: Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by....Idware when processor vectors to interrupt routine. TR1: Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off. TFO: Timer O overflow Flag. Set by hardware on Timer/Counter 0 overflow. Cleared by hardware when processor vectors to interrupt routine. TRO: Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off. Figure 11-2. Timer 1 in Mode 1: 16-Bit Timer/Counter Lt 1 1 LL L Fosc +12+ +12 Att Overflow AUXR2 (Address=A6H, Auxiliary Register2, Reset Value=0000,0000B) 7 6 5 4 3 2 1 1 0 TOX12 T1X12 URMOX6 S2TRS2SMOD S2TX12S2CKOE TOCKOE e topt TL1 1 (8 Bits) TH12 (8 Bits) TF14 Timer 1 Interrupte T1X12 T1 Pin die CAT 1 TR1 TOX12: Timer O clock source select while C/-T=0. Set to select Fosc as the clock source, and clear to select Fosc/12 as the clock source. T1X12: Timer 1 clock source select while C/-T=0. Set to select Fosc as the clock source, and clear to select Fosc/12 as the clock source. TOCKOE: Set/clear to enable/disable Timer O clock-out function from P3.4.- L -GATE L /INT1 pine The four operating modes are described in the following text. L * Fosc is the system clock 11.1.1 Mode 0: 13-Bit Timer/Counter L 11.1.3 Mode 2: 8-Bit Auto-Reload L Timer 0 and Timer 1 in Mode 0 look like an 8-bit Counter with a divide-by-32 prescaler. And, Mode 0 operation is the same for these two timers. Figure 11-1 shows the Mode 0 operation. In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all Os, it sets the Timer interrupt flag TFx. The counted input is enabled to the Timer when TRX=1 and either GATE=0 or /INTx=1. (Setting GATE=1 allows the Timer to be controlled by external input /INTx, to facilitate pulse width measurements). TRX and TFX are control bits in SFR TCON. The GATE bit is in TMOD. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3). Mode 2 configures the Timer register as an 8-bit Counter (TLx) with automatic reload, as shown in Figure 11-3. Overflow from TLX not only sets TFx, but also reloads TLX with the contents of THx, which is preset by software. The reload leaves THX unchanged. Figure 11-3. Timer 1 in Mode 2: 8-Bit Auto-Reload The 13-bit register consists of all 8 bits of THx and the lower 5 bits of TLx. The upper 3 bits of TLx are indeterminate and should be ignored. Setting the run flag (TRX) does not clear these registers. That is to say the user should initialize THX an TLx before start counting L LLLL1 L L L Figure 11-1. Timer 1 in Mode 0: 13-Bit Timer/Counter Overflow TL1 (8 Bits) TF1CH Timer 1 Interrupte T1X124 Fosc +124 T1 Pin I cite L TR14 TL TH1 Overflow (5 Bitsy (8 Bits) - TF1+ Timer 1 Interrupte TH1e (8 Bits) GATE ortopot dt GATED T1X12 T1 Pin L /INT1 pin CAT TR14 * Fosc is the system clock GATE o r LLLLLLL L INTO pine /INT1 pine