MIPS Assembly (Simple)

The MIPS architecture supports byte and halfword (16-bit) memory transfer operations. The instructions are load byte (lb), load byte unsigned (lbu), store byte (sb), load halfword (lh), load halfword unsigned (lhu) and store halfword (sh). Code: char a, b;//8-bit variables (a @ address 100) (b @ address 200) Part a) Assuming 8-bit operations are supported (lb, lbu, sb), write a MIPS code that swaps the variables a and b. Part b) If MIPS doesn't support byte and halfword operations, then we can only use 'load word' (lw) and 'store word' (sw), which are 32-bit operations. Accordingly, rewrite the code above using only (lw, sw) as memory transfer instructions