Modify the VHDL code in Figure 7.52 by adding a parameter that sets the number of flip-flops in the counter.

436 CHAPTER 7 FLIP-FLOPS, REGISTERS, COUNTERS, AND A SIMPLE PROCESSOR LIBRARY ieee USE ieee.std logic.1164.all USE ieee.std.logic.unsigned.all; ENTITY upcount IS PORT (Clock, Resetn, E IN STD.LOGIC : OUT STD LOGIC VECTOR (3 DOWNTO 0)) END upcount ARCHITECTURE Behavior OF upcount IS BEGIN SIGNAL Count: STD LOGIC VECTOR (3 DOWNTO 0); PROCESS (Clock. Resetn) BEGIN IF Resetn = '0, THEN Count