module TestBench$()$;

reg clk$\_$enable, reset, preset$\_023,$ CLK;

wire $[15$:$0]$ Rand$\_$out;

Main DUT$0($Rand$\_$out, CLK$,$ clk$\_$enable, reset, preset$\_023)$;

Lsfr DUT$1()$;

always begin

#$10$

CLK $=0$;

#$10$

CLK $=1$;

end

initial begin

clk$\_$enable $=0$;

reset $=0$;

preset$\_023=0$;

#$15$

$display$("$Rand$\_$out $=\%$b$",$ Rand$\_$out$)$;

#$10$

$display$("$Rand$\_$out $=\%$b$",$ Rand$\_$out$)$;

$finish;

end

endmodulemodule Main$($Rand$\_$out, CLK$,$ clk$\_$enable, reset, preset$\_023)$;

output $[15$:$0]$ Rand$\_$out;

input clk$\_$enable, reset, preset$\_023,$ CLK;

wire and$\_0\_$out, $\backslash 1\_$Q $,\backslash 2\_$Q $,\backslash 3\_$Q $,\backslash 4\_$Q $,\backslash 5\_$Q $,\backslash 6\_$Q $,\backslash 7\_$Q $,\backslash 8\_$Q $,\backslash 9\_$Q $,\backslash 10\_$Q $,\backslash 11\_$Q $,\backslash 12\_$Q $,\backslash 13\_$Q $,\backslash 14\_$Q $,\backslash 15\_$Q $,$ xor$\_0\_$out, xor$\_1\_$out, xor$\_2\_$out, $\backslash 0\_$Q ;

wire $[15$:$0]$ Splitter$\_0\_$cmb;

assign and$\_0\_$out $=$ clk$\_$enable & CLK;

DflipFlop $\backslash 1(\backslash 1\_$Q $,,$ and$\_0\_$out, $\backslash 0\_$Q $,$ reset, $,)$;

DflipFlop $\backslash 2(\backslash 2\_$Q $,,$ and$\_0\_$out, $\backslash 1\_$Q $,$ reset, preset$\_023,)$;

DflipFlop $\backslash 3(\backslash 3\_$Q $,,$ and$\_0\_$out, $\backslash 2\_$Q $,$ reset, preset$\_023,)$;

DflipFlop $\backslash 4(\backslash 4\_$Q $,,$ and$\_0\_$out, $\backslash 3\_$Q $,$ reset, $,)$;

DflipFlop $\backslash 5(\backslash 5\_$Q $,,$ and$\_0\_$out, $\backslash 4\_$Q $,$ reset, $,)$;

DflipFlop $\backslash 6(\backslash 6\_$Q $,,$ and$\_0\_$out, $\backslash 5\_$Q $,$ reset, $,)$;

DflipFlop $\backslash 7(\backslash 7\_$Q $,,$ and$\_0\_$out, $\backslash 6\_$Q $,$ reset, $,)$;

DflipFlop $\backslash 8(\backslash 8\_$Q $,,$ and$\_0\_$out, $\backslash 7\_$Q $,$ reset, $,)$;

DflipFlop $\backslash 9(\backslash 9\_$Q $,,$ and$\_0\_$out, $\backslash 8\_$Q $,$ reset, $,)$;

DflipFlop $\backslash 10(\backslash 10\_$Q $,,$ and$\_0\_$out, $\backslash 9\_$Q $,$ reset, $,)$;

DflipFlop $\backslash 11(\backslash 11\_$Q $,,$ and$\_0\_$out, $\backslash 10\_$Q $,$ reset, $,)$;

DflipFlop $\backslash 12(\backslash 12\_$Q $,,$ and$\_0\_$out, $\backslash 11\_$Q $,$ reset, $,)$;

DflipFlop $\backslash 13(\backslash 13\_$Q $,,$ and$\_0\_$out, $\backslash 12\_$Q $,$ reset, $,)$;

DflipFlop $\backslash 14(\backslash 14\_$Q $,,$ and$\_0\_$out, $\backslash 13\_$Q $,$ reset, $,)$;

DflipFlop $\backslash 15(\backslash 15\_$Q $,,$ and$\_0\_$out, $\backslash 14\_$Q $,$ reset, $,)$;

assign Splitter$\_0\_$cmb $=\{\backslash 15\_$Q $,\backslash 14\_$Q $,\backslash 13\_$Q $,\backslash 12\_$Q $,\backslash 11\_$Q $,\backslash 10\_$Q $,\backslash 9\_$Q $,\backslash 8\_$Q $,\backslash 7\_$Q $,\backslash 6\_$Q $,\backslash 5\_$Q $,\backslash 4\_$Q $,\backslash 3\_$Q $,\backslash 2\_$Q $,\backslash 1\_$Q $,\backslash 0\_$Q $\}$;

assign Rand$\_$out $=$ Splitter$\_0\_$cmb;

assign xor$\_0\_$out $=\backslash 13\_$Q $^\backslash 15\_$Q ;

assign xor$\_1\_$out $=\backslash 12\_$Q $^$ xor$\_0\_$out;

assign xor$\_2\_$out $=\backslash 10\_$Q $^$ xor$\_1\_$out;

DflipFlop $\backslash 0(\backslash 0\_$Q $,,$ and$\_0\_$out, xor$\_2\_$out, reset, preset$\_023,)$;

endmodule

module Lsfr$()$;

endmodule

module DflipFlop$($q$,$ q$\_$inv, clk$,$ d$,$ a$\_$rst$,$ pre, en$)$;

parameter WIDTH $=1$;

output reg $[$WIDTH$-1$:$0]$ q$,$ q$\_$inv;

input clk$,$ a$\_$rst$,$ pre, en;

input $[$WIDTH$-1$:$0]$ d;

always @ $($posedge clk or posedge a$\_$rst$)$

if $($a$\_$rst$)$ begin

q $<=\text{'}$b$0$;

q$\_$inv $<=\text{'}$b$1$;

end else if $($en $==0)$ ;

else begin

q $<=$ dYou will need to edit the design file so that the DD flipflop works the same as it does in

$($code to use the $$preset$\_023$ signal must be integrated into the $$reset$$ if

statement$).$

e$.$ Run a simulation to generate $10$ numbers

f$.$ Hand in your list of numbers in both binary and hexadecimal format.